Abstract: A method of creating a prototype data processing system, by configuring a hardware development chip (HDC) according to user-defined settings, building user-defined logic adapted to function with the configured development chip, and allowing for the re-configuration of the HDC and user-defined logic after debugging. The HDC has several data processing macros including a processor core macro, a ROM emulation macro, a memory macro, and a bus macro. The macros may be configured by a configuration pin block which is connected to external configuration pins on the HDC. Customer logic is built using a field programmable gate array, which is interconnected with external ports of the HDC. The HDC and customer logic are verified using a debug port on the HDC, which is connected to a debug workstation. The invention allows a user to easily and quickly debug an application-specific integrated circuit (ASIC) design with a unique version of selected processor cores.

Abstract: Disclosed is a system and method of providing performance analysis on integrated circuit devices and systems using an IEEE JTAG 1149.1 interface. An integrated circuit device is described that includes an execution control register for receiving a control code from an external device via the JTAG interface, a means for selecting and coupling to one or more specific logic circuits on the device, one or more counters for recording specific events occurring on the logic circuits, and a counter register for managing the counter data and outputting it via the JTAG interface.