Abstract: A method and apparatus for reconfiguring an integrated circuit based on testing results is accomplished by an integrated circuit that includes a first circuit, a second circuit, and configuration circuitry deposited on a single die. After testing of the die, the configuration circuitry configures the integrated circuit based on the results of the testing. If both circuits passed the testing, the configuration circuitry couples, where appropriate, the first and second circuits together. If, however, the first circuit failed the testing and the second circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the second circuit were present on the die. If, however, the second circuit failed the testing and the first circuit passed the testing, the configuration circuitry configures the integrated circuit as if only the first circuit were present on the die.

Abstract: A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.

Abstract: A computer system is comprised of at least one of a main bus and an attached expansion bus, a CPU connected to the main bus, peripherals connected to one of the main bus or to the expansion buses, a subsystem connected to a bus for receiving control, address and data signals from the CPU comprising a graphics controller, a data compression circuit, a video controller, a memory connected to data input ports of the circuits and controllers via a subsystem bus having a bandwidth sufficient to carry video and graphics display signals, a first arbiter for determining which controller is permitted access the memory, a link bus connecting each of the controllers, and apparatus for providing polling signals to each of the controllers and circuits on the link bus and for receiving acknowledgement signals therefrom, and thereby synchronizing and allowing exchange of control information between the controllers and circuits.