Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: A signal intelligence system comprising a plurality of software components that are programmable to provide a signal intelligence function. The signal intelligence system includes a processor system having a plurality of interconnected processor devices and a plurality of processor managers that are connected to the processor devices and are configured to control software components associated with the processor devices.

Abstract: A signal intelligence system comprising a plurality of software components that are programmable to provide a signal intelligence function. The signal intelligence system includes a processor system having a plurality of interconnected processor devices and a plurality of processor managers that are connected to the processor devices and are configured to control software components associated with the processor devices. Further, the signal intelligence system has a framework manager that is configured to interact with the plurality of processor managers to control the processor devices and effectuate the signal intelligence function.

Abstract: A signal intelligence system comprising a plurality of software components that are programmable to provide a signal intelligence function. The signal intelligence system includes a processor system having a plurality of interconnected processor devices and a plurality of processor managers that are connected to the processor devices and are configured to control software components associated with the processor devices. Further, the signal intelligence system has a framework manager that is configured to interact with the plurality of processor managers to control the processor devices and effectuate the signal intelligence function.

Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing.

Abstract: A reconfigurable compute engine interconnect fabric includes a reconfigurable interconnect layer (24, FIG. 2) between an application layer (22) and a physical layer (26) which identifies the input and output pins for the engine and their functions.

Abstract: In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing.

Abstract: In a communications or jamming system, accurate timing for the control of the frequency, amplitude, modulation type, pulse repetition rate or other transmit characteristics is achieved for the transmission of digitally processed packetized signals through the use of standard non-realtime off-the-shelf components for the digital processing and a realtime interface which reads transmit chain headers and, with the assistance of a precise time reference, assures that the transmit chain is configured in time to transmit the packets. Note that the realtime interface assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components used in upstream digital processing.

Abstract: A reconfigurable distributed signal processing system uses an object-oriented component-framework architecture in which the system permits large-scale software reuse. This is accomplished by the use of a framework and a number of reusable, reconfigurable software components that are hardware independent.

Abstract: A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD). A shell configuration called a ‘wrapper’ has a standard look, feel and form factor that provides the interface between the high density language (HDL) application and a standardized and board independent HDL shell, thus isolating the HDL core. A second wrapper is a board specific HDL shell that interacts with the standardized shell. Any application that has the same look, feel and form factor has a common interface that allows various system boards to communicate, providing a mechanism for creating a HDL application component independent of the hardware. An outer shell binds the system to some board and talks to the application program interface (API) layer and the code layer to the outside world, such as the operating system.

Abstract: A layered mechanism for integrating programmable devices into software based frameworks for distributed processing wherein the software framework interfaces with an adaptation layer, which in turn interfaces with a programmable device, such as a field programmable gate array (FPGA).

Abstract: A reconfigurable distributed signal processing system uses an object-oriented component-framework architecture in which the system permits large-scale software reuse. This is accomplished by the use of a framework and a number of reusable, reconfigurable software components that are hardware independent. The components communicate over a data fabric using open published APIs over one or more data communications mechanisms. Interchangeable software components are used that perform the signal processing. Interchangeability is assured by each component meeting a required interface in which the component inherits the required interface elements from component base classes. This use of inheritance to assure interface compliance also reduces the programming work required for developing a component. Most importantly, the interchangeable components are reconfigurable into various systems at runtime, as defined by a Plan.

Abstract: A multi-level framework that allows an application to be developed independent of the chip or board, and any dependency is built in as part of the framework of the field programmable device (FPD). A shell configuration called a ‘wrapper’ has a standard look, feel and form factor that provides the interface between the high density language (HDL) application and a standardized and board independent HDL shell, thus isolating the HDL core. A second wrapper is a board specific HDL shell that interacts with the standardized shell. Any application that has the same look, feel and form factor has a common interface that allows various system boards to communicate, providing a mechanism for creating a HDL application component independent of the hardware. An outer shell binds the system to some board and talks to the application program interface (API) layer and the code layer to the outside world, such as the operating system.

Abstract: In a communications or jamming system, accurate timing of the transmission of digitally processed signals is accomplished through the use of standard off-the-shelf components. In order to eliminate the need for high-cost, difficult to develop, specific digital hardware or realtime synchronous software not available from the standard off-the-shelf components, the output from the non-real time components is coupled to a realtime interface that assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components. In one embodiment, the signals to be transmitted are digitized and then packetized, with the data to be transmitted reconstructed using non-real time digital processing.

Abstract: In a communications or jamming system, accurate timing for the control of the frequency, amplitude, modulation type, pulse repetition rate or other transmit characteristics is achieved for the transmission of digitally processed packetized signals through the use of standard non-realtime off-the-shelf components for the digital processing and a realtime interface which reads transmit chain headers and, with the assistance of a precise time reference, assures that the transmit chain is configured in time to transmit the packets. Note that the realtime interface assures nanosecond timing accuracy regardless of timing errors introduced by the off-the-shelf components used in upstream digital processing.

Abstract: A receiver employs fast-Fourier-transform modules to process the received signals in the frequency domain. It samples the input signal at a high sampling rate to cover a broad input bandwidth, but it transforms the sampled input signals in short segments, segments that cover time durations considerably shorter than the duration of the impulse response of the receiver's tuner filter. The transform of the sampled input signal is multiplied by a Gaussian transfer function to reduce the amount of information contained in the signal, and the values of the resultant frequency-domain sequence are reordered in such a manner as to correspond to resampling in the time domain at a slower rate. This results in coverage of the time duration of an input segment by a relatively small number of samples.

Abstract: A system for indicating the direction of a source of radio waves received by a circular antenna array (12) includes a Butler matrix (18) that receives the array outputs and feeds the resultant matrix outputs to correction circuits (22) whose transfer functions are the inverses of the direction-independent factors of antenna patterns generated by antenna elements driven at relative phases that advance around the array at rates that complete an integral number of cycles in one circuit of the array. The resultant corrected signals are fed to a compressive receiver (26), which accordingly generates an output on an output port whose position indicates the direction of the source of the signal.

Abstract: The sweep rate of a linearly swept frequency generator is increased while maintaining strict linearity by artificially increasing the number of zero axis crossings of the output signal from a linearly swept voltage controlled oscillator over those that would naturally occur during a linear sweep. This permits an increased sampling rate which, in turn, permits the oscillator sweep rate to be increased without loss of accuracy. Increasing the number of zero axis crossings is accomplished by introducing phase shifts in the output of the oscillator at calculated sampling times with phase shifting being accomplished indirectly by heterodyning the swept oscillator output with the output from a fixed oscillator whose output signal is phase shifted by discrete amounts during the frequency sweep. Only a small number of phase shifts need be introduced due to the discovery of certain symmetries of phase when sweeping through a frequency range.

Abstract: A method and apparatus are provided for sorting signals from compressive receivers in accordance with the type of modulation on the signal, so as to be able to establish the identity of the signal short of fully demodulating it. It has been found that signals from a compressive receiver which are insufficiently sampled for complete demodulation can be identified by "histograms" in which each designated condition, such as the number of consecutive 1's or 0's is graphed against the number of occurrences of this designated condition over a period of time, designated a "data collection interval." The result is a pattern or diagram which is characteristic of the modulation type, such that FSK, DFSK, PSK, hand morse, machine morse, anomolous morse, AM, SSB, and multitones can be distinguished one from another. Moreover, it is possible to recognize two-way voice communication.