Abstract: A CN.sup.2 memory testing circuit for generating a sequence of C(N.sup.2 +1) memory addresses which will accomplish a CN.sup.2 test with the least possible memory transitions. In one embodiment for an odd integer C, the mth bit in the memory address sequence comprises at least one repetition of a unique transition bit (UTB) pattern, where the UTB pattern comprisesUTB Pattern=(C+1)/2 entries of 00, concatenated with C-1 entries of 10, concatenated with (C+1)/2 entries of 11, to yield the transitions 0-0, 0-1, 1-0, and 1-1. The m+1th bit in this memory address sequence comprisesm+1th bit pattern=a plurality of different combinations of 00, 01, 10, and 11, in any order, but with each of the different bit combinations aligned, at least once, with each different transition in the UTB pattern.A second embodiment, with an even integer C, is similar to the first embodiment, but with a UTB pattern comprisingUTB pattern=C(2).sup.2m-1 entries of 00, concatenated with C(2).sup.2m-1 entries of 01, concatenated with C(2).