Abstract: A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physical address is performed in which the number of levels in the hierarchy depends upon whether the linear address is an extended linear address.

Abstract: Maximum throughput or "back-to-back" scheduling of dependent instructions in a pipelined processor is achieved by maximizing the efficiency in which the processor determines the availability of the source operands of a dependent instruction and provides those operands to an execution unit executing the dependent instruction. These two operations are implemented through number of mechanisms. One mechanism for determining the availability of source operands, and hence the readiness of a dependent instruction for dispatch to an available execution unit, relies on the prospective determination of the availability of a source operand before the operand itself is actually computed as a result of the execution of another instruction. Storage addresses of the source operands of an instruction are stored in a content addressable memory (CAM).

Abstract: A processor is disclosed comprising a front end circuit that fetches a series of instructions according to a program sequence determined by at least one branch prediction, a register renaming circuit that allocates execution resources to each instruction, and an execution circuit that executes each instruction in the instruction stream. The execution circuit causes the front end circuit to refetch the series of instructions if a branch misprediction is detected. A stall signal disables the register renaming circuit until the execution circuit commits the branch result to an architectural state according to the program sequence.

Abstract: Each member system of a distributed collection of self-monitoring hardware systems includes receiving logic operative to receive a wellness token from a first other hardware system of the distributed collection of hardware systems. Each member system also includes modification logic, communicatively coupled to the receiving logic, operative to modify the wellness token to create a modified wellness token in a manner that reflects the wellness of the member hardware system, and transmitting logic, communicatively coupled to the modification logic, operative to transmit the modified wellness token to a second other hardware system of the distributed collection of hardware systems.

Abstract: A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, the flags used by these instructions are renamed. In general, a RAT unit provides register renaming to provide a larger physical register set than would ordinarily be available within a given macroarchitecture's logical register set (such as the Intel architecture or PowerPC or Alpha designs, for instance) to eliminate false data dependencies between instructions that reduce overall superscalar processing performance for the microprocessor. The renamed flag registers contain several flag bits and various flag bits may be updated or read by different instructions.

Abstract: A method and circuitry for coordinating exceptions in a processor. The processor generates a result data value and an exception data value for each instruction wherein the exception data value specifies whether the corresponding instruction causes an exception. The processor commits the result data values to an architectural state of the processor in the sequential program order, and fetches an exception handler to processes the exception if the exception is indicated by one of the exception data values. The processor fetches an asynchronous event handler to processes an asynchronous event if the asynchronous event is detected while the result data values are committed to the architectural state of the processor.

Abstract: A mechanism for efficiently overlapping multiple operand types is used in a microprocessor which includes a plurality of execution units and a mechanism to provide operations, which include one or more operands, to the plurality of execution units. Each of the plurality of execution units interprets the one or more operands as different types of operands, and the mechanism to provide operations overlaps the different types of operands.

Abstract: This invention overcomes the address size backward compatibility problem by first subtracting the segment base address from the linear destination address of a branch instruction to generate a virtual destination address. It is assumed that the branch instruction destination address is n bits long with m most significant bits. It is desired to provide backward compatibility in the n-bit processor for branch instruction code written for processors utilizing instruction address fields of size (n-m) bits. After obtaining the virtual address, if any of the m most significant bits are non-zero, then those m bits are set to zero to thereby generate a corrected virtual address. If such a compatibility correction is necessary, then a clear signal is asserted to flush all state of the processor that resulted from instructions being fetched after the branch instruction was fetched. The corrected virtual address is added back to the segment base address to generate a corrected linear address.

Abstract: A mechanism for indicating within a register alias table (RAT) that certain data has become architecturally visible so that the RAT contains the most recent location of the certain data. Upon receiving the indication that data associated with a particular register is architecturally visible, if a subsequent operation uses the particular register as a source, the data will be supplied from the architecturally visible buffer instead of from an internal buffer (not architecturally visible). The internal buffer is implemented by a reorder buffer (ROB) which contains information associated with instructions that have not yet retired. The architecturally visible buffer is a retirement register file (RRF) which contains information associated with retired instructions.

Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.

Abstract: A circuit comprising a number of range registers and complimentary decoding/matching circuits is provided to a processor for determining the memory type of a physical address, thereby allowing memory operating characteristics to be determined as soon as the physical address is available in an execution stage preceding cache access. Additionally, a memory type field is provided to each address translation lookaside buffer entry of the data and instruction memory subsystem for storing the determined memory type, and the memory type determination circuit is disposed in the page miss handler, thereby allowing memory type to be determined at the same time when the physical address is determined.

Abstract: A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-order processing. Resources within the microprocessor include a store buffer, a load buffer, a reorder buffer and a reservation station. The reorder buffer contains a larger set of physical registers and also contains information related to speculative instructions and the reservation station comprises information related to instructions pending execution. The load buffer is only allocated to load instructions and is valid for an instruction from allocation pipestage to instruction retirement. The store buffer is only allocated to store instructions and is valid for an instruction from allocation to store performance.

Abstract: A computer system including a processor having a inherently weakly-ordered memory model comprising a mechanism for emulating strong-ordering to produce self-consistent ordering on a system-wide basis. The processor snoops the system bus externally to determine if a STORE on the external bus hits a LOAD buffer inside the memory subsystem of the processor. If so, the situation is flagged as one which carries the risk of violating processor ordering rules. When the STORE hits the same LOAD address in the LOAD buffer of the processor's memory subsystem, the speculative state of the processor is erased. This cancels the LOAD operation in all subsequent operations. The processor then begins executing from the aborted LOAD; this time loading the newly updated value.

Abstract: A simplified method and apparatus for handling the change of instruction control flow in a microprocessor is provided. Rather than attempting to implement a change in the instruction flow immediately, the processor first recognizes that flow is to be redirected from a predicted instruction flow to a correct instruction flow according to a flow control indicator. The flow control indicator may be attached to instructions flowing down the pipeline or inserted as a separate instruction in the pipeline. The pipeline is cleared of state created by instructions that do not follow the correct instruction flow, i.e., instructions that were erroneously fetched after the instruction causing the change in flow. The change in flow as indicated by the flow control indicator is implemented later in the pipeline.

Abstract: A data processor includes a plurality of physical registers and a decoder that decodes a stream of instructions into micro-operations which include speculative operations specifying associated logical registers. The data processor further includes a register-alias table having a plurality of addressable entries corresponding to logical registers, specified by the speculative operations. Each entry of the register-alias table contains a register pointer to a corresponding physical register. The processor further includes a retirement register file that maintains register values of non-speculative operations, and a retirement array that maintains a retirement ordering for the retirement register file. Both the register-alias table and retirement array are updated by circuitry that is responsive to a register exchange operation; the circuitry swapping register pointers associated with first and second entries, respectively.

Abstract: A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an instruction cache memory lookup to fetch the multiple instructions, performing instruction length decoding on the instructions, rotating the instructions, and decoding the instructions. The present invention also performs register renaming, allocates resources and sends a portion of each of the operations to a buffering mechanism (e.g., a reservation station). The instruction cache memory lookup, instruction length decoding, rotation and decoding of the instructions, as well as the register renaming, are performed in consecutive pipestages.The present invention provides for executing the instructions in an out-of-order pipeline. The execution produces results.

Abstract: A method and apparatus for instruction refetch in a processor is provided. To ensure that a macro instruction is available for refetching after the processor has handled an event or determined a correct restart address after a branch misprediction, an instruction memory includes an instruction cache for caching macro instructions to be fetched, and a victim cache for caching victims from the instruction cache. To ensure the availability of a macro instruction for refetching, the instruction memory (the instruction cache and victim cache together) always stores a macro instruction that may need to be refetched until the macro instruction is committed to architectural state. A marker micro instruction is inserted into the processor pipeline when an instruction cache line is victimized. The marker specifies an entry in the victim cache occupied by the victimized cache line.

Abstract: A speculative execution out of order processor comprising a reorder circuit containing a plurality of physical registers that buffer speculative execution results for integer and floating-point operations, and a real register circuit containing a plurality of committed state registers that buffer committed execution results for either integer or floating-point operations, depending on the register. The reorder and real register circuits read the speculative and committed source data values for incoming micro-ops, and transfer the speculative and committed source data values over to a micro-op dispatch circuit over a common data path. A retire logic circuit commits the speculative execution results to an architectural state by transferring the speculative execution results from the reorder circuit to the real register circuit.

Abstract: Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.

Abstract: A Register Alias Table (RAT) for floating point and integer register renaming within a superscalar microprocessor. The RAT provides register renaming of integer and floating point registers and flags to take advantage of a larger physical register set than would ordinarily be available within a given macroarchitecture (such as the Intel architecture or Power PC or Alpha designs) and thereby eliminate false data dependencies that reduce overall superscalar processing performance. As uops are simultaneously presented to the RAT logic, their logical sources (both floating point and integer) are used as indices into a RAT array to look up the corresponding physical registers which reside within a Re-Order Buffer (ROB) where the data for these logical source is found. The ROB is composed of many multiple-bit physical registers. During the same clock cycle, the RAT array is updated with new physical destinations granted by an Allocator such that uops in future cycles can read them for their physical sources.