Abstract: A driving logic circuit having input and output terminals and first and second power terminals is described in combination with an interfacing means for making the driving logic circuit compatible with a driven logic circuit. This is accomplished by providing a first D.C. power source means which is connected across the first and second power terminals, and a second D.C. power source means which is connected in opposition to the first D.C. power means. With this arrangement the D.C. power to the power terminals is shifted to the extent of the voltage of the second D.C. power source means so as to be made compatible with the driving voltages required to drive the driven logic circuit.

Abstract: A memory addressing system which enables a computer to address a total of 048,575 words (32 times its original capacity) with minimal impact upon existing software. The method employed by this invention involves a new dual usage of the b (index) designator in each instruction word so that in addition to its normal function of specifying which of 8 index registers is to be added to the address portion of the instruction, it also specifies which of 8 base registers is to be arithmetically added to the basic 15-bit address to determine the final 20-bit absolute memory location address. A total of 262,144 words may be accessed by this dual use of the b designator for any one setting of the base registers. Each program module is designed to operate in a 32,768 word environment and no coding changes need be made to it; the computer operator need only maintain the appropriate offset values in the base registers for the module currently in operation.