Patents by Inventor Robert P. Davidson
Robert P. Davidson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10319815Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.Type: GrantFiled: May 26, 2014Date of Patent: June 11, 2019Assignee: NXP USA, Inc.Inventors: Xiaowei Ren, Robert P. Davidson, Mark A. DeTar
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Patent number: 9123804Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.Type: GrantFiled: June 11, 2014Date of Patent: September 1, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
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Publication number: 20140284716Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a first well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a second well region adjacent the first well region, having the second conductivity type, and having a higher dopant concentration than the first well region, to establish a path to carry charge carriers of the second conductivity type away from a parasitic bipolar transistor involving a junction between the channel region and the source region.Type: ApplicationFiled: June 11, 2014Publication date: September 25, 2014Applicant: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
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Publication number: 20140252467Abstract: Embodiments of laterally diffused metal oxide semiconductor (LDMOS) transistors are provided. An LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth.Type: ApplicationFiled: May 26, 2014Publication date: September 11, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: XIAOWEI REN, ROBERT P. DAVIDSON, MARK A. DETAR
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Patent number: 8772870Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.Type: GrantFiled: October 31, 2012Date of Patent: July 8, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
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Patent number: 8753948Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.Type: GrantFiled: October 31, 2011Date of Patent: June 17, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Xiaowei Ren, Robert P. Davidson, Mark A. Detar
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Publication number: 20140117446Abstract: A device includes a semiconductor substrate, source and drain regions in the semiconductor substrate and having a first conductivity type, a gate structure supported by the semiconductor substrate between the source and drain regions, a well region in the semiconductor substrate, having a second conductivity type, and in which a channel region is formed under the gate structure during operation, and a shunt region adjacent the well region in the semiconductor substrate and having the second conductivity type. The shunt region has a higher dopant concentration than the well region to establish a shunt path for charge carriers of the second conductivity type that electrically couples the well region to a potential of the source region.Type: ApplicationFiled: October 31, 2012Publication date: May 1, 2014Inventors: Xiaowei Ren, David C. Burdeaux, Robert P. Davidson, Michele L. Miera
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Publication number: 20130105892Abstract: A lateral diffused metal oxide semiconductor (LDMOS) transistor is provided. The LDMOS transistor includes a substrate having a source region, channel region, and a drain region. A first implant is formed to a first depth in the substrate. A gate electrode is formed over the channel region in the substrate between the source region and the drain region. A second implant is formed in the source region of the substrate; the second implant is laterally diffused under the gate electrode a predetermined distance. A third implant is formed to a second depth in the drain region of the substrate; the second depth is less than the first depth. A method for forming the LDMOS transistor is also provided.Type: ApplicationFiled: October 31, 2011Publication date: May 2, 2013Inventors: XIAOWEI REN, Robert P. Davidson, Mark A. Detar
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Patent number: 5528202Abstract: A technique for achieving impedance transformations utilizing transmission lines has been provided. This technique involves placing additional distributed capacitance along the length of a transmission line thereby reducing the effective characteristic impedance of the transmission line. The effective wavelength for the transmission line is also reduced thereby substantially reducing the electrical length of a quarter wavelength matching network and making the transmission line practical and effective even at low frequencies.Type: GrantFiled: December 23, 1994Date of Patent: June 18, 1996Assignee: Motorola, Inc.Inventors: Daniel D. Moline, Robert P. Davidson
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Patent number: 4985686Abstract: An active load impedance control system for a radio frequency power amplifier comprising an amplification means for amplifying radio frequency signals and providing a forward signal, a control means responsive to the operating conditions of said amplification means, a correction signal means responsive to the control means for providing an amplitude, a sampling means and phase controlled corrective reflective signal and a combining means for combining said forward signal and said corrective reflective signal.Type: GrantFiled: December 4, 1989Date of Patent: January 15, 1991Assignee: Motorola, Inc.Inventors: Robert P. Davidson, Richard A. Rose
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Patent number: 4320509Abstract: A logic structure for an LSI digital circuit includes data compression circuitry for deriving a signature word from the data on a multiplicity of internal nodes which are not directly accessible from the terminals of the circuit. The signature word provides error information concerning the data on the internal nodes which are not otherwise available for testing purposes. The addition of data compression circuitry facilitates the testing of LSI digital circuits and can be complemented with minimal overhead chip area.Type: GrantFiled: October 19, 1979Date of Patent: March 16, 1982Assignee: Bell Telephone Laboratories, IncorporatedInventor: Robert P. Davidson