Abstract: A current limit circuit (10/40) for controlling a power transistor (12) has been provided. The current limit circuit includes circuitry which is responsive to a voltage appearing across the drain and source electrodes of the power transistor for providing an appropriate voltage at the gate electrode of the power transistor when a load is de-coupled from the power transistor. This has the effect of preventing excessive transient current when the load is subsequently coupled to the power transistor. Additionally, the current limit circuit includes circuitry for limiting the current flowing through the power transistor via a sense circuit when the load is coupled to the power transistor.

Abstract: A two stage gate drive circuit (10) for controlling a power transistor (12) has been provided. The drive circuit includes a first stage (14) coupled to a first supply voltage terminal for providing a high current drive signal to the power transistor for quickly switching on the power transistor. However, once the power transistor is turned on, the first stage becomes inactive and a second stage (16) coupled to a second supply voltage terminal provides a low current drive signal to the power transistor for fully enhancing the power transistor and lowering its on resistance. The gate drive circuit further includes a timer circuit (18) for rendering the first stage active for predetermined period of time.

Abstract: A bipolar complementary metal oxide semiconductor (BICMOS) sense circuit for sensing data on read data lines during a read cycle of a memory comprises a load portion and a sense amplifier portion. In one form, the load portion couples true and complement read data lines to a first voltage in response to a start of a read cycle. When the true and complement read data lines exceed a predetermined voltage, the sense amplifier is enabled. The load portion becomes inactive when the voltage on the read data lines reaches approximately the first voltage. Then a selected memory cell provides a differential voltage on a bit line pair, which is coupled to the read data lines, indicating the contents of the selected memory cell. The sense amplifier provides a differential current onto a corresponding read global data line pair in response to the differential voltage.

Abstract: A BiMOS voltage reference circuit which includes a bandgap circuit for providing a predetermined voltage at an output of the circuit that is independent of temperature. A start-up and bias circuit coupled to the bandgap circuit for providing a start-up current to the bandgap circuit during power-up and for providing a bias current to the bandgap circuit after power-up. A feedback circuit coupled to the bandgap circuit for maintaining the bias current to the bandgap circuit independent of power supply variations wherein the predetermined voltage at the output of the circuit is also independent of power supply variations as well as temperature.

Abstract: A circuit is provided that generates a predetermined regulated voltage between first and second terminals that is positioned between first and second power supply voltage rails wherein the predetermined regulated voltage is substantially independent of temperature and power supply variation. The circuit includes a bandgap circuit for providing a predetermined reference potential that is substantially independent of temperature and power supply variation. A resistive circuit provides first and second voltages which are referenced with respect to the first supply voltage rail. A level translator circuit translates the second voltage provided by the resistive circuit to a third voltage which is referenced with respect to the second supply voltage rail.

Abstract: A FM mobile radio is disclosed which is capable of future functional expansion due to a unique microprocessor hardware/software control system. The radio includes a control microprocessor which is capable of performing all the basic radio control functions. In addition, options are added via a plug-on board that includes an option microprocessor which interfaces with the control microprocessor over a data bus and with the radio's audio circuits through audio processing circuitry. The software of the system allows control to be passed to the option board. The radio operates in a standard control mode and an option control mode. In the standard mode, in which no option board is present, the control processor performs all basic radio control functions. In the option mode, where the option control microprocessor is present, the main control processor typically receives commands from the option board.

Abstract: Received power line trip signals are delayed in their tripping function by a circuit which causes introduction of the delay in response to a wideband received signal rising rapidly above a dynamic amplitude level, or in response to a narrowband received signal going outside upper and lower amplitude limits. Either condition could indicate a false trip signal, so that a delay before actual tripping is desirable.

Abstract: The compressor part of a compander uses a differential amplifier to receive voice signals. Diode attenuator circuits are connected to the differential amplifier output and attenuate the differential amplifier output signals as a function of a rectified signal derived from the compressor output. The expander part of the compander also uses a differential amplifier to receive voice signals. The differential amplifier is interconnected by a diode attenuator circuit which varies the gain of the differential amplifier as a function of a rectified signal derived from the expander input. The compander thus requires no inductors and uses components which are relatively small and compact.