Patents by Inventor Robert P. Fabinski

Robert P. Fabinski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8728722
    Abstract: A method for producing a device in one or more layers of patternable material disposed over a substrate uses multiple exposure tools having different resolution limits and maximum expose field sizes. An abutting field pattern is exposed and stitched in one layer of patternable material using one exposure tool and a first mask. A periphery pattern is then exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The maximum expose field of the first exposure tool is smaller than a size of the device while the maximum expose field of the second exposure tool is at least as large as, or larger, the size of the device so that the combination of the stitched abutting field pattern and the periphery pattern forms a complete pattern in the patternable material.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: May 20, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran, Joseph R. Summa
  • Patent number: 8728713
    Abstract: A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: May 20, 2014
    Assignee: Truesense Imaging, Inc.
    Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran
  • Patent number: 8415175
    Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: April 9, 2013
    Assignee: Truesense Imaging, Inc.
    Inventors: Shen Wang, Robert P. Fabinski, James E. Doran, Laurel J. Pace, Eric J. Meisenzahl
  • Patent number: 8415813
    Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.
    Type: Grant
    Filed: June 15, 2011
    Date of Patent: April 9, 2013
    Assignee: Truesense Imaging, Inc.
    Inventors: Shen Wang, Robert P. Fabinski, James E. Doran, Laurel J. Pace, Eric J. Meisenzahl
  • Publication number: 20120322271
    Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Inventors: Shen Wang, Robert P. Fabinski, James E. Doran, Laurel J. Pace, Eric J. Meisenzahl
  • Publication number: 20120319307
    Abstract: A semiconductor wafer includes multiple dies and a die identification region adjacent to or on each die. The die identification region can include a wafer indicator and a pattern of die locations representing die locations on the wafer. A die identification marker is provided in each pattern of die locations in the die identification region specifying a location of a respective die on the wafer.
    Type: Application
    Filed: June 15, 2011
    Publication date: December 20, 2012
    Inventors: Shen Wang, Robert P. Fabinski, James E. Doran, Laurel J. Pace, Eric j. Meisenzahl
  • Publication number: 20120082937
    Abstract: A method for producing a device in one or more layers of patternable material disposed over a substrate uses multiple exposure tools having different resolution limits and maximum expose field sizes. An abutting field pattern is exposed and stitched in one layer of patternable material using one exposure tool and a first mask. A periphery pattern is then exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The maximum expose field of the first exposure tool is smaller than a size of the device while the maximum expose field of the second exposure tool is at least as large as, or larger, the size of the device so that the combination of the stitched abutting field pattern and the periphery pattern forms a complete pattern in the patternable material.
    Type: Application
    Filed: August 2, 2011
    Publication date: April 5, 2012
    Inventors: Robert P. Fabinski, Eric J. Meisenzahl, James E. Doran
  • Publication number: 20120082938
    Abstract: A method for producing a measurement structure for measuring alignment of patterns formed in one or more layers of patternable material uses multiple exposure tools having different resolution limits and maximum expose field sizes. The measurement structure includes multiple complementary and coincident parts. An abutting field pattern is exposed and stitched in a layer of patternable material using a first exposure tool and a first mask. The abutting field pattern includes a first portion of the multiple complementary parts. A periphery pattern is exposed in the same layer or in a different layer of patternable material using a second exposure tool and a second mask. The periphery pattern includes a second portion of the multiple complementary parts. A maximum expose field of the first exposure tool is smaller than the maximum expose field of the second exposure tool.
    Type: Application
    Filed: August 2, 2011
    Publication date: April 5, 2012
    Inventors: Robert P. Fabinski, Eric Meisenzahl, James Doran
  • Patent number: 8022452
    Abstract: A source/drain region of a transistor or amplifier is formed in a substrate layer and is connected to a voltage source. A glow blocking structure is formed at least partially around the source/drain region and is disposed between the source/drain region and an imaging array of an image sensor. A trench is formed in the substrate layer adjacent to and at least partially around the source/drain region. The glow blocking structure includes an opaque material formed in the trench and one or more layers of light absorbing material overlying the source/drain region and the opaque material.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: September 20, 2011
    Assignee: Omnivision Technologies, Inc.
    Inventors: Shen Wang, Robert P. Fabinski, Robert Kaser
  • Publication number: 20100148231
    Abstract: A source/drain region of a transistor or amplifier is formed in a substrate layer and is connected to a voltage source. A glow blocking structure is formed at least partially around the source/drain region and is disposed between the source/drain region and an imaging array of an image sensor. A trench is formed in the substrate layer adjacent to and at least partially around the source/drain region. The glow blocking structure includes an opaque material formed in the trench and one or more layers of light absorbing material overlying the source/drain region and the opaque material.
    Type: Application
    Filed: December 12, 2008
    Publication date: June 17, 2010
    Inventors: Shen Wang, Robert P. Fabinski, Robert Kaser
  • Patent number: 7522203
    Abstract: An image sensor includes a substrate having a plurality of photosensitive sites for capturing an image and a plurality of additional photosensitive sites adjacent the image capturing photosensitive sites in which there is no image capture; and a digital signal embedded in one or more of the additional photosensitive sites for the purpose of identification.
    Type: Grant
    Filed: October 1, 2003
    Date of Patent: April 21, 2009
    Assignee: Eastman Kodak Company
    Inventors: Robert P. Fabinski, Laurence J. Lobel
  • Patent number: 7402882
    Abstract: A charge coupled device includes a substrate; a plurality of image pixels arranged in a two dimensional array in the substrate for capturing an electronic representation of an image and for transferring charge in a first direction; a transfer mechanism for transferring charge in a second direction from the plurality of the image pixels for further processing; an amplifier structure disposed in the substrate that receives the charge from the transfer mechanism and converts the charge into a voltage signal; a first opaque layer spanning over the amplifier for blocking near-infrared light inherently generated by an electrical field within the amplifier structure when a voltage is applied; and a second opaque layer deposited into the substrate for also blocking near-infrared light inherently generated by an electrical field within the amplifier structure when a voltage is applied.
    Type: Grant
    Filed: August 23, 2004
    Date of Patent: July 22, 2008
    Assignee: Eastman Kodak Company
    Inventors: Shen Wang, William F. DesJardin, Robert P. Fabinski, David N. Nichols, Christopher Parks, Eric G. Stevens
  • Patent number: 6870168
    Abstract: A method for creating a pattern on a substrate, the method includes the steps of imprinting a first pattern on the substrate; and imprinting a second substantially similar pattern which is mis-registered with regard to the first pattern so that the combination of the first and second patterns cause a systematic variation in a final size of defined elements across the substrate.
    Type: Grant
    Filed: November 12, 2003
    Date of Patent: March 22, 2005
    Assignee: Eastman Kodak Company
    Inventors: Robert P. Fabinski, Joseph R. Summa