Patents by Inventor Robert P. Gardyne

Robert P. Gardyne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10477226
    Abstract: A method and system for gracefully reducing demands for shared decompression resources required to present multiple video streams concurrently such that their streaming video content is simultaneously available for further processing or display. In particular, it relates to the use of presentation time stamps or incoming frames with reference to a time base dock and a threshold to determine if the decompression resources are falling behind in their ability to process incoming frames in real time. If this occurs then frames are dropped, i.e. discarded without being decompressed, with preference given to dropping incremental frames rather than key frames.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: November 12, 2019
    Assignee: Jupiter Systems, LLC
    Inventors: Tzvetan Mikov, Stanislav Angelov, Robert P. Gardyne
  • Publication number: 20170257636
    Abstract: A method and system for gracefully reducing demands for shared decompression resources required to present multiple video streams concurrently such that their streaming video content is simultaneously available for further processing or display. In particular, it relates to the use of presentation time stamps or incoming frames with reference to a time base dock and a threshold to determine if the decompression resources are falling behind in their ability to process incoming frames in real time. If this occurs then frames arc dropped, i.e. discarded without being decompressed, with preference given to dropping incremental frames rather than key frames.
    Type: Application
    Filed: May 22, 2017
    Publication date: September 7, 2017
    Inventors: Tzvetan Mikov, Stanislav Angelov, Robert P. Gardyne
  • Patent number: 5835145
    Abstract: A conversion system for converting run-level pairs into variable length codes (VLCs) for purposes of compression, where each run-level pair includes a run and level value derived from scanning blocks of DCT coefficients. Each run value is provided to a programmable memory, which stores a segment address table comprising a list of base addresses, where a base address is included for each valid run value. An adder is provided for adding the base address to the level value of the run-level pair for determining a VLC address. The VLC address is provided to another programmable memory, which stores a table of VLCs, where the VLCs are grouped according to corresponding run values into a plurality of run segments, where each run segment corresponds to one run value and where each group of VLCs are ordered according to level values. The VLCs are preferably organized in ascending order based on the level values.
    Type: Grant
    Filed: January 19, 1996
    Date of Patent: November 10, 1998
    Assignee: LSI Logic Corporation
    Inventors: Chi Ouyang, Robert P. Gardyne
  • Patent number: 5559532
    Abstract: A display system displays a cursor on a monitor using parallel pixels of video data. A hardware cursor processor receives a sequence of clock signals, cursor data, parallel video data arranged in P logical pixels per clock signal, and cursor position data. The hardware cursor processor provides composite video data representative of the cursor data and the video data to a memory. The composite video data is arranged in P logical pixels per clock signal. The hardware cursor processor arranges the cursor data within the P logical pixels per clock signal in response to the cursor position data. The cursor position data includes a position signal HPOS indicative of the horizontal position of the cursor on the screen and includes a preset signal HPRE indicative of the horizontal offset of the cursor. The cursor data is arranged within the P logical pixels of the composite video data to begin at the logical pixel equal to [(HPOS-HPRE) modulus P].
    Type: Grant
    Filed: November 10, 1994
    Date of Patent: September 24, 1996
    Assignee: LSI Logic, Inc.
    Inventor: Robert P. Gardyne