Abstract: A DRAM control circuit accommodates different speed grade DRAMs by modifying the RAS strobe. A number of wait states are inserted into a DRAM access cycle, having a start time and an end time, between the start and the end time of the access cycle. When the number of wait states inserted is zero, the RAS is deasserted at a first time relative to the end of the access cycle. When the number of wait states is at least one, the RAS is deasserted at a second time, earlier than the first time, relative to the end time of the access cycle, thereby increasing the row address strobe precharge time.

Abstract: A computer system is presented having a mechanism for re-mapping memory address space after system initiation. The mechanism includes a microcontroller embodying an integrated RAM controller and chip select unit. Select logic chooses between output from the chip select unit or output from the RAM controller, depending upon the state of memory chip select registers. The registers are set based upon whether a portion of the memory address space comprises ROM. If the space comprises ROM, then chip select signals are selected. After system initiation, data within ROM can be copied to a RAM, or loaded over a local or distal network, and the select logic chooses RAM controller output to operate the RAM.