Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Technologies for analyzing power state transitions of a processor of computing device including determining, by the computing device, a power state entered by the processor of the computing device and a duration of the power state entered based on power state records, wherein the power state records comprise transition data indicative of transitions of a processor of the computing device between power states. The computing device further determines an accuracy of a power state selection of the processor of the computing device based on the determined power state entered and target residency data for the processor. The target residency data identifies, for each power state of a plurality of power states of the processor, an amount of time required in the corresponding power state to result in a conservation of power.

Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

Abstract: Various embodiments are generally directed to generating logs recording events related to wakelocks at application and kernel levels, and then temporally aligning graphs of those events in a visual presentation to enable debugging of wakelocks. An apparatus to debug wakelocks includes a processor component; a capture component to intercept calls associated with application level wakelocks, the intercepted calls received by an application power manager of an operating system from application routines; and a relaying component to cooperate with the application power manager to provide indications of the intercepted calls to a system log generator of the operating system coupled to the application power manager, the system log generator to generate system log data comprising indications of events associated with execution of the operating system by the processor component and the indications of the intercepted calls. Other embodiments are described and claimed.

Abstract: Method, apparatus, and system for monitoring performance within a processing resource, which may be used to modify user-level software. Some embodiments of the invention pertain to an architecture to allow a user to improve software running on a processing resources on a per-thread basis in real-time and without incurring significant processing overhead.

Abstract: A system and method are described for configuring and collecting performance counter information of a computer system. The method includes providing one or more performance objects, each object containing a predetermined set of events. A user is allowed to select the entire set or a subset of events to be monitored during a collection session from the predetermined set of events contained in the performance objects. The performance counters associated with the subset of events selected are programmed to increment in response to an occurrence of a respective event. The data stored in each of the performance counters associated with the subset of events selected is periodically read during the collection session.

Abstract: A metal, especially silver, may be recovered from its alloy with lead by a method comprising injecting, into the molten alloy, an oxygen-containing gas to oxidize the lead to form lead oxide slag and removing the slag from the molten metal. The oxygen-containing gas is injected into the molten metal through an elongate consumable lance which extends lengthwise of itself from the interior to the exterior of the furnace and which is capable of being fed lengthwise from the exterior to the interior of the furnace through the guide tube as the lance is consumed in the furnace. The lance comprises a first elongate tube for the oxygen-containing gas and a second elongate tube located annularly about the first tube, for a coolant gas. A gas is also injected through the guide tube into the furnace to seal the lance. Also disclosed is a furnace suitable for use in the method.