Patents by Inventor Robert P. Ottavi
Robert P. Ottavi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7961877Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: GrantFiled: December 14, 2006Date of Patent: June 14, 2011Assignee: Intel CorporationInventors: Vinodh Gopal, Erdinc Ozturk, Matt Bace, Wajdi Feghali, Robert P. Ottavi
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Patent number: 7912886Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: GrantFiled: December 14, 2006Date of Patent: March 22, 2011Assignee: Intel CorporationInventors: Vinodh Gopal, Wajdi Feghali, Gilbert M. Wolrich, Daniel Cutter, Robert P. Ottavi
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Patent number: 7664915Abstract: An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.Type: GrantFiled: December 19, 2006Date of Patent: February 16, 2010Assignee: Intel CorporationInventors: Vinodh Gopal, Gilbert Wolrich, Kirk S. Yap, Wajdi K. Feghali, John Vranich, Robert P. Ottavi
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Patent number: 7607068Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: GrantFiled: August 31, 2006Date of Patent: October 20, 2009Assignee: Intel CorporationInventors: Vinodh Gopal, Gilbert M. Wolrich, Daniel Cutter, Wajdi Feghali, Robert P. Ottavi
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Publication number: 20080147768Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method includes loading a first word of a vector from memory into a first register and subsequently loading the first word from the first register to a second register. The method may also include loading a second word into the first register and loading at least one bit from the second register into an arithmetic logic unit. The method may further include performing modular exponentiation on the at least one bit to generate a result and generating a public key based upon, at least in part, the result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTEL CORPORATIONInventors: Vinodh Gopal, Wajdi Feghali, Gilbert Wolrich, Daniel Cutter, Robert P. Ottavi
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Publication number: 20080144810Abstract: The present disclosure provides a system and method for performing modular exponentiation. The method may include dividing a first polynomial into a plurality of segments and generating a first product by multiplying the plurality of segments of the first polynomial with a second polynomial. The method may also include generating a second product by shifting the contents of an accumulator with a factorization base. The method may further include adding the first product and the second product to yield a first intermediate result and reducing the first intermediate result to yield a second intermediate result. The method may also include generating a public key based on, at least in part, the second intermediate result. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: December 14, 2006Publication date: June 19, 2008Applicant: INTEL CORPORATIONInventors: Vinodh Gopal, Erdinc Ozturk, Matt Bace, Wajdi Feghali, Robert P. Ottavi
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Publication number: 20080148025Abstract: An acceleration unit offloads computationally intensive tasks from a processor. The acceleration unit includes two data processing paths each having an Arithmetic Logical Unit and sharing a single multiplier unit. Each data processing path may perform configurable operations in parallel on a same data. Special multiplexer paths and instructions are provided to allow P and Q type syndromes to be computed on a stripe in a single-pass of the data through the acceleration unit.Type: ApplicationFiled: December 19, 2006Publication date: June 19, 2008Inventors: Vinodh Gopal, Gilbert Wolrich, Kirk S. Yap, Wajdi K. Feghali, John Vranich, Robert P. Ottavi
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Publication number: 20080140753Abstract: An electronically implemented method includes multiplying a number A, and a number B, where A is composed of segments ai and B is composed of segments bj where i and j are integers greater than 1. The multiplying includes determining partial product values for at least some of aibj and determining a sum of partial product values for aibj and ajbi where ai=bj and bj=ai for respective values of i and j, by multiplying one of (1) aibj and (2) ajbi by two. A sum is determined and stored in a memory storage element of the determined partial product values and the determined sum of partial product values for aibj and ajbi.Type: ApplicationFiled: December 8, 2006Publication date: June 12, 2008Inventors: Vinodh Gopal, Gilbert M. Wolrich, Wajdi Feghali, Robert P. Ottavi
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Publication number: 20080059865Abstract: The present disclosure provides an apparatus and method for generating a Galois-field syndrome. One exemplary method may include loading a first data byte from a first storage device to a first register and loading a second data byte from a second storage device to a second register; ANDing the most significant bit (MSB) of the first data byte and a Galois-field polynomial to generate a first intermediate output; XORing each bit of the first intermediate output with the least significant bits (LSBs) of the first data byte to generate a second intermediate output; MUXing the second intermediate output with each bit of the first data byte to generate a third intermediate output; XORing each bit of the third intermediate output with each bit of the second data byte to generate at a fourth intermediate output; and generating a RAID Q syndrome based on, at least in part, the fourth intermediate output. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.Type: ApplicationFiled: August 31, 2006Publication date: March 6, 2008Applicant: INTEL CORPORATIONInventors: Vinodh Gopal, Gilbert M. Wolrich, Daniel Cutter, Wajdi Feghali, Robert P. Ottavi
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Patent number: 7206858Abstract: A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.Type: GrantFiled: September 19, 2002Date of Patent: April 17, 2007Assignee: Intel CorporationInventors: Donald F. Hooper, Serge Kornfeld, Robert P. Ottavi, John C. Cole
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Publication number: 20040059828Abstract: A method and apparatus for transmitting network traffic includes selecting a major node in a major ring, where the major node corresponds to a first transmission opportunity encoded in the major ring. The major node specifies a minor node in a minor ring representing a virtual port. The method and apparatus also includes transmitting network traffic to a virtual connection that uses the virtual port. Alternatively, transmitting network traffic involves processing a schedule that includes a sequence of transmission opportunities encoded in a schedule ring and satisfying a minimum data rate for a scheduled virtual connection by processing a corresponding first minimum number of transmission opportunities from the schedule, each such transmission opportunity allocated by a schedule node to the scheduled virtual connection, where the schedule node is included in the schedule ring.Type: ApplicationFiled: September 19, 2002Publication date: March 25, 2004Inventors: Donald F. Hooper, Serge Kornfeld, Robert P. Ottavi, John C. Cole