Abstract: A digital programmable packet switch synchronizer receives a digital input data stream which includes a unique digital word. The unique digital word is stored in the synchronizer in a random access memory. A group of the most recently received data bits are stored in memory along with a blanker bit for each data bit. The blanker bit determines the valid or invalid status of the data bit. During each bit period of the incoming data stream, the stored data bits are serially compared with the stored unique word. A count is made of the number of noncomparisons between the stored data bits and the stored unique word bits when the data bit is valid. If the number of noncomparisons does not exceed a programmed error limit, an output signal is generated to indicate detection of the unique word. A similar count is carried out for detection of the inverse to the unique word.