Abstract: A structure and an improved isolation trench between active regions within the semiconductor substrate involves forming on a silicon substrate and forming a nitride layer on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into a portion of the trench liner to form an oxynitride layer. After formation of the oxynitride layer, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Abstract: A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.

Abstract: The present disclosure relates to a chemical vapor deposition system including a chemical vapor deposition chamber, and a circlet wafer positioned within the chemical vapor deposition chamber. The circlet wafer is mounted on a rotatable member that at least partially extends through an opening of the wafer. A drive mechanism is used to rotate the rotatable member and the circlet wafer. The system also includes a gas injector for injecting reactive gases toward the circlet wafer. The present disclosure also relates to a chemical vapor deposition system including a chemical vapor deposition chamber, a wafer positioned within the chemical vapor deposition chamber, and a gas injector for injecting first and second reactive gases toward the wafer. The gas injector includes a mixing region for mixing the first and second reactive gases before the first and second reactive gases are discharged from the gas injector.

Abstract: A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.

Abstract: A method is provided for forming a multi-level interconnect in which capacitive coupling between laterally adjacent conductors employed by an integrated circuit is reduced. According to an embodiment, a conductor is dielectrically spaced above a semiconductor substrate, and a masking structure is arranged upon an upper surface of the conductor. Select portions of the conductor are removed such that opposed ends of the masking structure extend beyond opposed sidewall surfaces of the conductor. An interlevel dielectric is deposited to a level above the masking structure such that air gaps are formed laterally adjacent the opposed sidewall surfaces of the conductor, and the interlevel dielectric is planarized to a level spaced above an upper surface of the masking structure.

Abstract: An apparatus for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.

Abstract: An integrated circuit and a method of making a transistor thereof are provided. The method includes the steps of forming a first stack on the substrate and a second stack on substrate in spaced-apart relation to the first stack, where the first stack has a first layer and first and second spacers adjacent to the first layer and the second stack has a second layer and third and fourth spacers adjacent to the second layer. A gate dielectric layer is formed on the substrate between the first and second stacks and a first conductor layer is formed on the gate dielectric layer. A first source/drain region is formed beneath the first conductor layer and a second source/drain region is formed beneath the second conductor layer. The first and second layers are removed and a first contact is formed on the first source/drain region and a second contact is formed on the second source/drain region.

Abstract: A semiconductor device is formed by forming a sacrificial plug over a substrate and forming active regions in the substrate adjacent the sacrificial plug. A film is then formed over portions of the substrate adjacent the sacrificial plug. The sacrificial plug is then selectively removed leaving an opening in the film, and a gate electrode is formed in the opening. The sacrificial plug can be formed from several materials including, for example, polysilicon and nitrogen-bearing species such as nitride. The gate electrode may, for example, be formed from temperature-sensitive metals such as copper since the gate electrode may be formed subsequent to high temperature steps of the fabrication, such as a source drain anneal, for example.

Abstract: A method of integrating lightly doped drain implantation for complementary metal oxide semiconductor (CMOS) device fabrication includes providing a semiconductor substrate having a p-well region and an n-well region. A patterned gate oxide and gate electrode are formed on each of the p-well region and the n-well region. One of either the p-well region or the n-well region is masked with a patterned photoresist having a prescribed thickness, leaving a non-masked region exposed. Ions are then implanted to form desired p-type lightly doped drain (Pldd) regions in the n-well region, including Pldd regions adjacent to edges of the gate electrode in the n-well region. Lastly, ions are implanted to form desired n-type lightly doped drain (Nldd) regions in the p-well region, including Nldd regions adjacent to edges of the gate electrode in the p-well region, the Pldd and Nldd regions thus being formed with the use of only a single ion implantation masking step.

Abstract: A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.

Abstract: A process for fabricating a device having a thin gate oxide layer on which a gate electrode is formed is disclosed. The thin gate oxide layer is formed using an ion implantation process in order to reliably control the thickness of the gate oxide layer. A nitrogen-containing species is used in the ion implantation in order to form a nitrogen rich oxide layer and to increase the reliability and performance of a resultant device.

Abstract: In a semiconductor device fabrication process, an active region of the semiconductor device is formed by doping an active region after formation of a relatively thick oxide layer. According to the process, a gate electrode is formed on a substrate and a relatively thick oxide layer is formed over the gate electrode. Portions of the relatively thick oxide layer are removed to expose a region of the substrate adjacent the gate electrode. The exposed region is then doped with a dopant to form an active region. The active region may form an LDD region. The relatively thick oxide layer may comprise a contact formation layer.

Abstract: A method of lithographically fabricating small line width features in a device in accordance with a desired pattern, the small line width features being smaller than that capable of a lithographic process alone, is disclosed. A first layer of material is provided upon a substrate, the first layer including that in which the small line width features are to be made. A lithographically patterned layer is then provided upon the first layer in accordance with a second pattern defined in conjunction with the desired pattern. The patterned layer includes a second material selected to be compatible with the material of the first layer. A conformal layer is then deposited upon the patterned layer, the conformal layer including a third material selected to be compatible in conjunction with the first material and with the second material.

Abstract: A method and structure are provided for an IGFET which has a highly scalable short conduction channel length. The short channel IGFET functions more rapidly than do longer conduction channel devices. Lightly doped regions provide a graded extension or buffer region to the conduction channel. Thus, the voltage drop is shared by the source/drain and channel, in contrast to an abrupt n+/p junction where the almost the entire voltage drop occurs across the lightly doped (channel) side of the junction. This method and structure preserves the integrity of the IGFET by protecting the gate from "hot electron injection." The method and structure provide an IGFET with increased performance without compromising the IGFET's reliability or longevity.

Abstract: Generally, the present invention relates to a semiconductor device having a dual thickness gate dielectric along the channel and a process of fabricating such a device. By providing a dual thickness gate dielectric, the gate dielectric can, for example, be optimized to the transistor and device performance can be enhanced.

Abstract: A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels. Thus, high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level. The interconnect achieves lower resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor. In order to abut the gate conductors together, the upper level transistor is inverted relative to the lower level transistor.

Abstract: A method for in-situ cleaning of polysilicon-coated quartz furnaces are presented. Traditionally, disassembling and reassembling the furnace is required to clean the quartz. This procedure requires approximately four days of down time which can be very costly for a company. In addition, cleaning the quartz requires large baths filled with a cleaning agent. These baths occupy a large amount of laboratory space and require a large amount of the cleaning agent. Cleaning the furnace in-situ eliminates the very time consuming procedure of assembling and disassembling the furnace and at the same time requires less laboratory space and less amount of cleaning agent. The polysilicon remover may be either a mixture of hydrofluoric and nitric acid or TMAH. TMAH is preferred because it less hazardous than hydrofluoric acid and compatible with more materials. The cleaning agent may be introduced into the furnace either from the built-in injectors or from additionally installed injectors.