Patents by Inventor Robert Paul Mikulka
Robert Paul Mikulka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10490348Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.Type: GrantFiled: June 24, 2016Date of Patent: November 26, 2019Assignee: QUALCOMM IncorporatedInventors: Mario Francisco Velez, Daeik Daniel Kim, Niranjan Sunil Mudakatte, David Francis Berdy, Changhan Hobie Yun, Jonghae Kim, Chengjie Zuo, Yunfei Ma, Robert Paul Mikulka
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Patent number: 10354795Abstract: A method includes forming a first conductive spiral and a second conductive spiral of a spiral inductor coupled to a substrate. The second conductive spiral overlays the first conductive spiral. A first portion of an innermost turn of the spiral inductor has a first thickness in a direction perpendicular to the substrate. The first portion of the innermost turn includes a first portion of the first conductive spiral and does not include the second conductive spiral. A second portion of the innermost turn includes a first portion of the second conductive spiral. A portion of an outermost turn of the spiral inductor has a second thickness in the direction perpendicular to the substrate. The second thickness is greater than the first thickness. The portion of the outermost turn includes a second portion of the first conductive spiral and a second portion of the second conductive spiral.Type: GrantFiled: August 19, 2016Date of Patent: July 16, 2019Assignee: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Chengjie Zuo, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Xiangdong Zhang, Jonghae Kim, Je-Hsiung Lan
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Patent number: 10290414Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.Type: GrantFiled: August 31, 2015Date of Patent: May 14, 2019Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, Mario Francisco Velez, Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Je-Hsiung Jeffrey Lan, Jonghae Kim, Niranjan Sunil Mudakatte, Robert Paul Mikulka
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Patent number: 10187031Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.Type: GrantFiled: May 10, 2016Date of Patent: January 22, 2019Assignee: QUALCOMM IncorporatedInventors: Yunfei Ma, Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Niranjan Sunil Mudakatte, Robert Paul Mikulka, Jonghae Kim
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Patent number: 10103703Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.Type: GrantFiled: May 20, 2016Date of Patent: October 16, 2018Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Jonghae Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Robert Paul Mikulka
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Patent number: 10074625Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.Type: GrantFiled: September 20, 2015Date of Patent: September 11, 2018Assignee: QUALCOMM IncorporatedInventors: Mario Francisco Velez, David Francis Berdy, Changhan Hobie Yun, Jonghae Kim, Chengjie Zuo, Daeik Daniel Kim, Je-Hsiung Jeffrey Lan, Niranjan Sunil Mudakatte, Robert Paul Mikulka
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Patent number: 10069474Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.Type: GrantFiled: April 25, 2016Date of Patent: September 4, 2018Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Je-Hsiung Jeffrey Lan, David Francis Berdy, Yunfei Ma, Robert Paul Mikulka, Jonghae Kim
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Patent number: 9966426Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.Type: GrantFiled: September 14, 2015Date of Patent: May 8, 2018Assignee: QUALCOMM IncorporatedInventors: Niranjan Sunil Mudakatte, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Chengjie Zuo, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
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Patent number: 9906318Abstract: An apparatus is disclosed that includes a frequency multiplexer circuit coupled to an input node and configured to receive an input signal via the input node. The frequency multiplexer circuit comprises a first filter circuit, a second filter circuit, and a third filter circuit. The apparatus also includes a switching circuit that is configurable to couple at least two of a first output of the first filter circuit, a second output of the second filter circuit, or a third output of the third filter circuit to a single output port.Type: GrantFiled: April 8, 2015Date of Patent: February 27, 2018Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Robert Paul Mikulka, Mario Francisco Velez, Jonghae Kim, Matthew Michael Nowak, Ryan Scott C. Spring, Xiangdong Zhang
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Patent number: 9876513Abstract: A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.Type: GrantFiled: March 31, 2016Date of Patent: January 23, 2018Assignee: QUALCOMM IncorporatedInventors: Changhan Hobie Yun, David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Robert Paul Mikulka
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Publication number: 20170372831Abstract: Disclosed is an apparatus including a plurality of vias each having a defined shape, wherein each of the plurality of vias includes a first two-dimensional conductive layer plated on a first side of a substrate, the first two-dimensional conductive layer having the defined shape, a second two-dimensional conductive layer plated on a second side of the substrate, the second two-dimensional conductive layer having the defined shape, and a via conductively coupling the first two-dimensional conductive layer to the second two-dimensional conductive layer. The apparatus further includes a plurality of interconnects configured to conductively couple the plurality of vias, wherein the first two-dimensional conductive layer and the second two-dimensional conductive layer of each of the plurality of vias are perpendicular to the plurality of interconnects.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: Mario Francisco VELEZ, Daeik Daniel KIM, Niranjan Sunil MUDAKATTE, David Francis BERDY, Changhan Hobie YUN, Jonghae KIM, Chengjie ZUO, Yunfei MA, Robert Paul MIKULKA
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Publication number: 20170338788Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.Type: ApplicationFiled: May 20, 2016Publication date: November 23, 2017Inventors: Changhan Hobie YUN, David Francis BERDY, Chengjie ZUO, Daeik Daniel KIM, Jonghae KIM, Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE, Robert Paul MIKULKA
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Publication number: 20170331445Abstract: A tunable matching network is disclosed. In a particular example, the matching network includes at least one first inductor in a signal path of the matching network. The matching network includes at least one second inductor outside of the signal path. The matching network includes one or more switches coupled to the at least one second inductor. The one or more switches are configured to selectively enable mutual coupling of the at least one first inductor and the at least one second inductor.Type: ApplicationFiled: May 10, 2016Publication date: November 16, 2017Inventors: Yunfei Ma, Chengjie Zuo, David Francis Berdy, Daeik Daniel Kim, Changhan Hobie Yun, Je-Hsiung Jeffrey Lan, Mario Francisco Velez, Niranjan Sunil Mudakatte, Robert Paul Mikulka, Jonghae Kim
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Publication number: 20170288707Abstract: A three dimensional (3D) multiplexer structure may include a first two dimensional (2D) inductor capacitor (LC) filter layer. The first 2D LC filter layer may include a first 2D spiral inductor and a first capacitor(s). The 3D multiplexer structure may also include a second 2D LC filter layer. The second 2D LC filter layer may include a second 2D spiral inductor and a second capacitor(s) stacked directly on and communicably coupled to the first 2D LC filter.Type: ApplicationFiled: March 31, 2016Publication date: October 5, 2017Inventors: Changhan Hobie YUN, David Francis BERDY, Chengjie ZUO, Daeik Daniel KIM, Mario Francisco VELEZ, Niranjan Sunil MUDAKATTE, Robert Paul MIKULKA
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Patent number: 9666362Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.Type: GrantFiled: February 17, 2016Date of Patent: May 30, 2017Assignee: QUALCOMM IncorporatedInventors: David Francis Berdy, Chengjie Zuo, Daeik Daniel Kim, Changhan Hobie Yun, Mario Francisco Velez, Robert Paul Mikulka, Jonghae Kim
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Patent number: 9660110Abstract: An apparatus includes a varactor having a first contact that is located on a first side of a substrate. The varactor includes a second contact that is located on a second side of the substrate, and the second side is opposite the first side. The apparatus further includes a signal path between the first contact and the second contact.Type: GrantFiled: September 26, 2014Date of Patent: May 23, 2017Assignee: QUALCOMM IncorporatedInventors: Daeik Daniel Kim, Jonghae Kim, Chengjie Zuo, Sang-June Park, Changhan Hobie Yun, Mario Francisco Velez, David Francis Berdy, Matthew Michael Nowak, Robert Paul Mikulka
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Publication number: 20170141756Abstract: A device includes an acoustic resonator embedded within an encapsulating structure that at least partially encapsulates the acoustic resonator. The device includes an inductor electrically connected to the acoustic resonator. At least a portion of the inductor is embedded in the encapsulating structure.Type: ApplicationFiled: April 25, 2016Publication date: May 18, 2017Inventors: Changhan Hobie Yun, Chengjie Zuo, Daeik Daniel Kim, Mario Francisco Velez, Niranjan Sunil Mudakatte, Je-Hsiung Jeffrey Lan, David Francis Berdy, Yunfei Ma, Robert Paul Mikulka, Jonghae Kim
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Publication number: 20170084565Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.Type: ApplicationFiled: September 20, 2015Publication date: March 23, 2017Inventors: Mario Francisco VELEZ, David Francis BERDY, Changhan Hobie YUN, Jonghae KIM, Chengjie ZUO, Daeik Daniel KIM, Je-Hsiung Jeffrey LAN, Niranjan Sunil MUDAKATTE, Robert Paul MIKULKA
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Publication number: 20170077214Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.Type: ApplicationFiled: September 14, 2015Publication date: March 16, 2017Inventors: Niranjan Sunil MUDAKATTE, Daeik Daniel KIM, David Francis BERDY, Changhan Hobie YUN, Je-Hsiung Jeffrey LAN, Chengjie ZUO, Mario Francisco VELEZ, Robert Paul MIKULKA, Jonghae KIM
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Publication number: 20170062120Abstract: A substrate includes a first dielectric layer, a magnetic core at least partially in the first dielectric layer, where the magnetic core comprises a first non-horizontal thin film magnetic (TFM) layer. The substrate also includes a first inductor that includes a plurality of first interconnects, where the first inductor is positioned in the substrate to at least partially surround the magnetic core. The magnetic core may further include a second non-horizontal thin film magnetic (TFM) layer. The magnetic core may further include a core layer. The magnetic core may further include a third thin film magnetic (TFM) layer, and a fourth thin film magnetic (TFM) layer that is substantially parallel to the third thin film magnetic (TFM) layer.Type: ApplicationFiled: August 31, 2015Publication date: March 2, 2017Inventors: Changhan Hobie Yun, Mario Francisco Velez, Chengjie Zuo, Daeik Daniel Kim, David Francis Berdy, Je-Hsiung Jeffrey Lan, Jonghae Kim, Niranjan Sunil Mudakatte, Robert Paul Mikulka