Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express (PCIe) compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.

Abstract: A system includes a host processor (105) and a peripheral device (708). The host processor (105) is coupled to the peripheral device (708) by a Peripheral Component Interconnect Express (PCIe) compliant link. The peripheral device (708) can include logic circuitry to identify, based on an application using the device and the host processor (105), a read to write ratio utilized by the application; and provide the read to write ratio to the host processor (105). The host processor (105) comprising logic circuitry to send a command signal to a device in communication with the hardware processor across a peripheral component interconnect express compliant link, the command signal indicating a transmission (TX) lane to receive (RX) lane ratio, the TX lane to RX lane ratio corresponding to the read to write ratio identified by the peripheral device (708); and receive an indication that the device is capable of supporting asymmetric TX and RX ratios.