Patents by Inventor Robert Pezzani

Robert Pezzani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7561408
    Abstract: A method for controlling an SCR-type switch, comprising applying to the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.
    Type: Grant
    Filed: December 3, 2003
    Date of Patent: July 14, 2009
    Assignee: STMicroelectronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 7432549
    Abstract: The invention relates to a vertical-type power switch disposed in a semi-conductor chip, comprising a winding (30) located on the periphery of at least one face of said chip. Said winding comprises two binding posts (31, 32) which supply a signal that is proportional to the current fluctuations in said switch.
    Type: Grant
    Filed: January 22, 2002
    Date of Patent: October 7, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 7433166
    Abstract: A constant current generator connected between first and second terminals includes a gate turn-off thyristor in series with a resistor; a current limiting component connected between the anode gate and the cathode gate of the thyristor; and a voltage reference connected between the cathode and the cathode gate of the thyristor.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: October 7, 2008
    Assignee: STMicroelectronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 7130455
    Abstract: A capacitive microsensor formed on a wafer, including a conductive detection area arranged on a first surface or front surface of the wafer; a conductive via crossing the wafer and emerging on said area; and a structure to ensure contact with said via on the second surface or rear surface of the wafer.
    Type: Grant
    Filed: March 13, 2002
    Date of Patent: October 31, 2006
    Assignee: STMicroeletronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 6862196
    Abstract: The invention concerns a control circuit for controlling a power switch by means of a galvanic insulation transformer, the transformer being produced in the form of planar conductive windings on an insulating substrate (20) whereon are integrated passive components constituting a high frequency excitation oscillating circuit for a primary winding of the transformer, the transformer substrate being directly mounted on a wafer (24) whereon is mounted a circuit chip (40) integrating the power switch.
    Type: Grant
    Filed: December 20, 2001
    Date of Patent: March 1, 2005
    Assignee: STMicroelectronics S.A.
    Inventors: Fabrice Guitton, Robert Pezzani
  • Patent number: 6791808
    Abstract: A clipping device intended for absorbing current peaks from 1 to 10 amperes, formed of a vertical NPN transistor, having an unconnected base, an emitter connected to a terminal on which positive voltage peaks are likely to appear, and a grounded collector, the transistor parameters being set so that it exhibits a negative dynamic resistance.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: September 14, 2004
    Assignee: STMicroelectronics S.A.
    Inventors: Eric Bernier, Robert Pezzani
  • Publication number: 20040135620
    Abstract: A method for controlling an SCR-type switch, consisting of applying on the switch gate several periods of an unrectified high-frequency voltage, the power of one HF halfwave being insufficient to start the SCR-type switch.
    Type: Application
    Filed: December 3, 2003
    Publication date: July 15, 2004
    Inventor: Robert Pezzani
  • Publication number: 20040056303
    Abstract: The invention relates to a vertical-type power switch disposed in a semi-conductor chip, comprising a winding (30) located on the periphery of at least one face of said chip. Said winding comprises two binding posts (31, 32) which supply a signal that is proportional to the current fluctuations in said switch.
    Type: Application
    Filed: July 22, 2003
    Publication date: March 25, 2004
    Inventor: Robert Pezzani
  • Patent number: 6580142
    Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: June 17, 2003
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Robert Pezzani
  • Patent number: 6573674
    Abstract: The invention concerns a control circuit for controlling a load to be supplied in alternating current voltage, comprising a two-way switch capable of being controlled by phase angle, in series with the load between two terminals applying the alternating current supply, and comprising, in parallel with the switch, a first resistive element, a first capacitor and an element, in series with the first resistive element and the first capacitor, and operating, in steady state conditions, as a constant current source, the midpoint of the association in series connection of the first resistive element and the first capacitor being connected, via an element with two-way conduction automatically triggered when the voltage at its terminals exceeds a predetermined threshold, to a terminal controlling the switch.
    Type: Grant
    Filed: May 16, 2001
    Date of Patent: June 3, 2003
    Assignee: STMicroelectronics S.A.
    Inventors: Bertrand Rivet, Robert Pezzani
  • Publication number: 20030075990
    Abstract: The invention concerns a control circuit for controlling a power switch by means of a galvanic insulation transformer, the transformer being produced in the form of planar conductive windings on an insulating substrate (20) whereon are integrated passive components constituting a high frequency excitation oscillating circuit for a primary winding of the transformer, the transformer substrate being directly mounted on a wafer (24) whereon is mounted a circuit chip (40) integrating the power switch.
    Type: Application
    Filed: October 9, 2002
    Publication date: April 24, 2003
    Inventors: Fabrice Guitton, Robert Pezzani
  • Patent number: 6552370
    Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: April 22, 2003
    Inventor: Robert Pezzani
  • Patent number: 6480056
    Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: November 12, 2002
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Robert Pezzani
  • Publication number: 20020130671
    Abstract: A capacitive microsensor formed on a wafer, including a conductive detection area arranged on a first surface or front surface of the wafer; a conductive via crossing the wafer and emerging on said area; and a structure to ensure contact with said via on the second surface or rear surface of the wafer.
    Type: Application
    Filed: March 13, 2002
    Publication date: September 19, 2002
    Inventor: Robert Pezzani
  • Patent number: 6411155
    Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.
    Type: Grant
    Filed: January 8, 2001
    Date of Patent: June 25, 2002
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Robert Pezzani
  • Publication number: 20020053939
    Abstract: The present invention relates to a triac network wherein each triac includes an N-type semiconductor substrate, containing a first thyristor comprised of NPNP regions and a second thyristor comprised of PNPN regions, and surrounded with a P-type deep diffusion. A P-type well contains an N-type region, on the front surface side. A first metallization corresponds to a first main electrode, a second metallization corresponds to a second main electrode, a third metallization covers the N-type region and is connected to a gate terminal, and a fourth metallization connects the P-type well to the upper surface of the deep diffusion.
    Type: Application
    Filed: December 27, 2001
    Publication date: May 9, 2002
    Inventor: Robert Pezzani
  • Publication number: 20010005302
    Abstract: A clipping device intended for absorbing current peaks from 1 to 10 amperes, formed of a vertical NPN transistor, having an unconnected base, an emitter connected to a terminal on which positive voltage peaks are likely to appear, and a grounded collector, the transistor parameters being set so that it exhibits a negative dynamic resistance.
    Type: Application
    Filed: December 22, 2000
    Publication date: June 28, 2001
    Inventors: Eric Bernier, Robert Pezzani
  • Patent number: 6252256
    Abstract: A design for an overvoltage protection circuit can be used to fabricate several different circuits incorporating different protection techniques. The design is suitable for use in a single device, which can be easily and inexpensively packaged and protected from the environment. Three terminal protection circuits can have three terminals on an upper surface of a substrate, or one terminal on a lower surface of the substrate, using a single modular design. Additional circuitry can be included to sense for high current conditions which are caused by overvoltages too low to trigger the normal overvoltage protection circuits.
    Type: Grant
    Filed: December 2, 1993
    Date of Patent: June 26, 2001
    Assignee: STMicroelectronics, Inc.
    Inventors: Angelo Ugge, Robert Pezzani
  • Publication number: 20010002870
    Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.
    Type: Application
    Filed: January 8, 2001
    Publication date: June 7, 2001
    Inventor: Robert Pezzani
  • Patent number: 6075277
    Abstract: A monolithic assembly includes vertical power semiconductor components formed throughout the thickness of a low doped semiconductive wafer of a first conductivity type, whose bottom surface is uniformly coated with a metallization. At least some of these components, so-called autonomous components, are formed in insulated sections of the substrate, whose lateral insulation is provided by a diffused wall of the second conductivity type and whose bottom is insulated through a dielectric layer interposed between the bottom surface of the substrate and the metallization.
    Type: Grant
    Filed: December 22, 1995
    Date of Patent: June 13, 2000
    Assignee: SGS-Thomas Microelectronics S.A.
    Inventor: Robert Pezzani