Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus detects a level of power received from each of a plurality of sources. The apparatus directs the power received from a first source to a charging circuit and directs the power received from at least a second source to the charging circuit. The apparatus directs the power received from the first source to the charging circuit by comparing the detected level of the power with a threshold and directing the power to the charging circuit based on a result of the comparison. The apparatus directs the power received from the at least a second source to the charging circuit by comparing the detected level of the power with the threshold and directing the power to the charging circuit based on a result of the comparison.

Abstract: In one embodiment, an electronic device includes an audio connector port comprising a ground terminal and one or more audio output terminals, a first audio amplifier coupled to one of the audio output terminals, and a multiplexer having an output terminal coupled to the input terminal of the first audio amplifier. Sense circuits inside the electronic device may be alternately coupled through the multiplexer and first audio amplifier so that, in a first mode of operation, the multiplexer couples the audio signal to the first audio output terminal, and in a second mode of operation, the multiplexer couples an analog voltage corresponding to an internally sensed value to the first audio output terminal. Use of the audio connector and audio circuitry to access internal electrical parameters may facilitate testing and analysis of internal systems.

Abstract: In one embodiment, an electronic device includes an audio connector port comprising a ground terminal and one or more audio output terminals, a first audio amplifier coupled to one of the audio output terminals, and a multiplexer having an output terminal coupled to the input terminal of the first audio amplifier. Sense circuits inside the electronic device may be alternately coupled through the multiplexer and first audio amplifier so that, in a first mode of operation, the multiplexer couples the audio signal to the first audio output terminal, and in a second mode of operation, the multiplexer couples an analog voltage corresponding to an internally sensed value to the first audio output terminal. Use of the audio connector and audio circuitry to access internal electrical parameters may facilitate testing and analysis of internal systems.

Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus are provided. The apparatus detects a level of power received from each of a plurality of sources. The apparatus directs the power received from a first source to a charging circuit and directs the power received from at least a second source to the charging circuit. The apparatus directs the power received from the first source to the charging circuit by comparing the detected level of the power with a threshold and directing the power to the charging circuit based on a result of the comparison. The apparatus directs the power received from the at least a second source to the charging circuit by comparing the detected level of the power with the threshold and directing the power to the charging circuit based on a result of the comparison.

Abstract: Aspects described herein are related to spintronic logic gates employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a spintronic logic gate is disclosed that includes a charge current generation circuit and a GSHE MTJ element. The charge current generation circuit is configured to generate a charge current representing an input bit set. The input bit set may include one or more input bit states for a logical operation. The GSHE MTJ element is configured to set a logical output bit state for the logical operation, and has a threshold current level. The GSHE MTJ element is configured to generate a GSHE spin current in response to the charge current and perform the logical operation on the input bit set by setting the logical output bit state based on whether the GSHE spin current exceeds the threshold current level.

Abstract: Aspects described herein are related to pipeline circuits employing a Giant Spin Hall Effect (GSHE) magnetic tunnel junction (MTJ) element(s) for performing logical operations. In one aspect, a pipeline circuit is disclosed. The pipeline circuit includes a first pipeline stage and a second pipeline stage. The first pipeline stage is configured to store a first bit set and to generate a first charge current representing the first bit set. The second pipeline stage includes a first GSHE MTJ element. The first GSHE MTJ element is configured to set a first bit state for the first logical operation, and has a first threshold current level. The first GSHE MTJ element is configured to generate a first GSHE spin current in response to the first charge current. In this manner, the first GSHE MTJ element is also configured to perform the first logical operation on the first bit set.