Abstract: A system and method for optimizing dispersion in an optical transmission line is provided. The system and method comprise measuring the amplitude of a d.c. voltage component of a synchronously demodulated data signal of at least one wavelength channel by an in-phase carrier at the baud frequency of the wavelength channel. In an alternative embodiment, the system and method comprise measuring the IF amplitude of the resulting a.c. signal of a data signal of the at least one wavelength channel comprising a received RZ signal mixed with a local oscillator, whose frequency differs from the wavelength channel baud by a relatively small amount, somewhere on the order of about 100 kHz.

Abstract: A system and method for optimizing dispersion in an optical transmission line is provided. The system and method comprise measuring the amplitude of a d.c. voltage component of a synchronously demodulated data signal of at least one wavelength channel by an in-phase carrier at the baud frequency of the wavelength channel. In an alternative embodiment, the system and method comprise measuring the IF amplitude of the resulting a.c. signal of a data signal of the at least one wavelength channel comprising a received RZ signal mixed with a local oscillator, whose frequency differs from the wavelength channel baud by a relatively small amount, somewhere on the order of about 100 kHz.

Abstract: A system and method for optimizing dispersion in an optical transmission line is provided. The system and method comprise measuring the amplitude of a d.c. voltage component of a synchronously demodulated data signal of at least one wavelength channel by an in-phase carrier at the baud frequency of the wavelength channel. In an alternative embodiment, the system and method comprise measuring the IF amplitude of the resulting a.c. signal of a data signal of the at least one wavelength channel comprising a received RZ signal mixed with a local oscillator, whose frequency differs from the wavelength channel baud by a relatively small amount, somewhere on the order of about 100 kHz.

Abstract: A wavelength-interchanging cross-connect for a wavelength-division multiplexing (WDM) optical communication system including both transparent optical paths and opaque paths through an electronic switching network, such as a high-speed digital cross-connect switch (DCS), including matching opto-electronic conversions of the data signal. All-optical switching is performed on the input and output sides, for example, by mechanically actuated fiber switches. The DCS, receiving optical inputs from the input optical switches and providing optical outputs to the output optical switches, performs switching in the electrical domain and can perform wavelength conversion of the signals passing through it. The DCS also provides for access to electrical add/drop lines for interfacing to a client. The transparent optical path, which can be either direct or through an optical switch, transfers a signal without regard to its format from the input to the output of the switching system.

Abstract: A method and a system for routing cells in an ATM switch. The switch which is input buffered, employs a multiplicity of crosspoint switch planes operating simultaneously in parallel, and whose outputs are combined by an output-buffered second stage. A traffic controlling or path assignment switching stage disposed before the crosspoint switch planes improves performance in the presence of correlated traffic. The switching stage may either control the traffic randomly or adaptively. Input concentration and output expansion functions within the switch are also disclosed. The use of an "unfair" or a predictable preference contention resolution device (CRD) in each of the crosspoint switch planes is possible in another embodiment of the invention. Advantages of the method and system include linear growth with large N in the size and complexity of both the switching circuits and the contention resolution circuits.

Abstract: A variable word length (VWL) decoder is disclosed in which an input bit stream of variable length words is input to a programmable logic array (PLA) (305) through an input shift register (302). The data association input plane (306) of the PLA compares the sequence of input bits in the register with all the possible variable length words. When a match is made, the PLA's length output plan (307) produces an output word representing the length of the detected variable length word and the PLA's word output plan (308) produces the fixed length word corresponding to the input VWL word. This fixed length word is input to a latch which is controlled by a downcounter (311). The length word is loaded into this downcounter, which decrements its count as the input bits are shifted through the register. Only when its count reaches zero have all bits of the previous variable length word been clocked through the shift register.

Abstract: The circuit phase aligns a phase-varying input data stream with a local clock. The data stream is sampled at the 0.degree. and 180.degree. phases of the local clock. Two pairs of outrigger samples which closely bracket the aforementioned primary samples are also obtained by the sextet sampler. Adjacent pairs of the six samples are applied to Ex-Or gates to yield disagreement signals which indicate the locations of data transitions relative to the samples. The primary samples (0.degree. and 180.degree.) are serially loaded into different halves of a biphase register, the taps of which provide the output with differently delayed versions of the input data at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals to a counter which determines which of the biphase register taps is connected to the output. The output is a replica of the input which is synchronized with the local clock.

Abstract: A Phase/Frequency Locked Loop comprises a controllable oscillator which is phase locked with the clock of an incoming non-return-to-zero digital data signal. The controllable oscillator may be a voltage-controlled oscillator (VCO) or may be purely digital. The circuitry includes a novel digital phase and frequency detector which detects both frequency and phase error by sampling the incoming data stream at multiple phases of the output of the VCO (or the digital equivalent thereof). One of two binary disagreement signals are produced depending on the sense of the phase error. During periods of frequency error, the circuit automatically selects the proper type of disagreement signal (the leading-edge disagreement) required to achieve frequency lock.

Abstract: This circuit phase aligns a phase-varying input data stream with a local clock. The incoming data stream is sampled at four quadrature points and these samples are applied to Ex-Or gates to yield four disagreement signals which indicates whether or not a transition from binary 0 to 1, or vise versa, has occurred between any pair of samples. The in-phase (0.degree.) and anti-phase (180.degree.) samples are serially loaded into different but similar shift registers, the taps of which provide the output with earlier or later versions of the input data stream at either 0.degree. or 180.degree.. A control circuit analyzes the disagreement signals and provides control signals which determine which of the shift register taps is connected to the aligner output. The circuit can correct for phase slippage between input data and local clock of up to plus or minus several time slots.

Abstract: An integrated circuit current source (10) has first (16) and second (30) current mirrors regeneratively coupled. The transistors (32, 34) of the second mirror (30) have unequal current densities, so that a resistor (40) connected to the emitter of the lower current density transistor (34) establishes a temperature-dependent output current. One of the transistors (18, 20, 34) has its base and emitter connected together through a modifying resistor (42, 53, 55) to modify the temperature dependence of the output. In one embodiment (10), the modifying resistor (42) connects the base and emitter of the lower current density transistor (34) and increases the temperature dependence of the output to make it directly proportional to the absolute temperature. Other embodiments (52, 54) are disclosed for obtaining both zero and negative temperature coefficient values for the output.

Abstract: An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.A circuit interconnects with input and output terminals for combining input and output signals into an intermediate signal having a magnitude equal to a weighted sum of the input and output signals. A frequency dependent circuit responds to the intermediate signal for producing a frequency dependent signal that is combined with the input signal to generate the output signal.

Abstract: An active variable equalizer is arranged to provide a Bode type variable equalizer characteristic without requiring an inductor. The equalization shape remains unchanged as the amount of equalization is varied. This equalizer uses a tandem arrangement of additive feedforward and negative feedback to achieve the mentioned equalization shape.