Abstract: A Graphene Hall sensor (GHS) is provided with a modulated gate bias signal in which the modulated gate bias signal alternates at a modulation frequency between a first voltage that produces a first conductivity state in the GHS and a second voltage that produces approximately a same second conductivity state in the GHS. A bias current is provided through a first axis of the GHS. A resultant output voltage signal is provided across a second axis of the Hall sensor that includes a modulated Hall voltage and an offset voltage, in which the Hall voltage is modulated at the modulation frequency. An amplitude of the Hall voltage that does not include the offset voltage is extracted from the resultant output voltage signal.

Abstract: A Graphene Hall sensor (GHS) may be provided with a modulated gate bias signal in which the modulated gate bias signal alternates at a modulation frequency between a first voltage that produces a first conductivity state in the GHS and a second voltage that produces approximately a same second conductivity state in the GHS. A bias current may be provided through a first axis of the GHS. A resultant output voltage signal may be provided across a second axis of the Hall sensor that includes a modulated Hall voltage and an offset voltage, in which the Hall voltage is modulated at the modulation frequency. An amplitude of the Hall voltage that does not include the offset voltage may be extracted from the resultant output voltage signal.

Abstract: A method of operating a memory circuit to reduce standby current is disclosed. The method includes applying a first voltage (Vdd) to a power terminal (224) of a memory cell having a first (612) and a second (614) data terminal. A data bit is stored in a memory cell (600,602,604,606). A second voltage (VDA) different from the first voltage is applied to the power terminal. A third voltage (Ground) is applied to the first and second data terminals. The first voltage is applied to the power terminal.

Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A refractory metal word line forms the gate of the access transistor at a hole in the polysilicon field plate.

Abstract: A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: A DRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: A memory cell comprises a semiconductor pillar comprising an inversion layer formed on a side wall of the pillar. A conductive capacitor of the memory cell comprises a first electrode formed by the inversion layer. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region comprising the inversion layer. The gate is coupled to a control line partially overlying a top end of the pillar.

Abstract: A dynamic one-transistor read/write memory cell employs a trench capacitor to increase the magnitude of the stored charge. The trench is etched into the silicon surface at a diffused N+ capacitor region similar in structure to the N+ bit line, then thick oxide is grown over the bit line and over the capacitor region, but not in the trench. The upper plate of the capacitor is a polysilicon layer extending into the trench and also forming field plate isolation over the face of the silicon bar. A word line forms the gate of the access transistor at a hole in the polysilicon field plate.

Abstract: A memory cell comprises a semiconductor pillar and an insulator on a sidewall of the pillar. A conductive capacitor of the memory cell comprises a first electrode adjacent the insulator. A transistor of the memory cell is formed in the pillar and comprises a first source/drain region, a gate, and a second source/drain region coupled to the first electrode.

Abstract: A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: A dRAM memory cell structure and a method for forming the same is disclosed. Each memory cell is formed at a pillar, where the storage plate is an inversion region created by a field plate surrounding all sides of each pillar and separated therefrom by a storage dielectric film. The field plate is formed in a grid shape, and is disposed at the bottom of the trenches surrounding the array of pillars to serve as the fixed plate for all storage capacitors in the array. At the top of each pillar is a diffusion to which the bit lines are connected. Disposed in the trench above the field plate and extending in one direction are word lines. Each word line is formed of a polysilicon filament onto which tungsten is deposited by way of selective CVD.

Abstract: An improved memory cell layout (54) is formed including a trench cell (60) formed in a semiconductor substrate (58). The memory cell layout (54) includes a bitline (56) and a wordline (62) for storing and accessing charge. The charge is stored on a capacitor formed from a conductor (68), an insulating region (70) and a semiconductor substrate (58). Bitline (56) is primarily tangential to a trench cell (60), or may surround the periphery thereof. A wordline (62) overlies trench cell (60) and extends therein, and further may be formed of a width narrower than trench cell (60).

Abstract: A trench (28) of a DRAM cell is formed in a (p-) epitaxial layer (10) and a silicon substrate (12), and a storage oxide (32) is grown on the sidewalls (30) of the trench (28). A highly doped polysilicon capacitor electrode (34) is formed in the trench (28). A portion (52) of the storage oxide (32) is removed from a selected side of the sidewalls (30), and a plug (68) is deposited therein and etched back so that the electrode (34) is connected to the epitaxial layer (10). A thermal cycle is used to diffuse dopant from the capacitor electrode (34) into and through the plug (68) and into the adjacent semiconductor layer (10) to make the plug (68) conductive and to form a source region (66) of a pass gate transistor of the cell.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide when opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: An integrated circuit capacitor is disclosed which has improved leakage and storage characteristics. The dielectric material for the capacitor consists of a first layer of silicon nitride adjacent the lower plate, such as a silicon substrate, upon which a layer of silicon dioxide is formed. A second layer of silicon nitride is formed over the silicon dioxide layer, above which the second plate is formed. The layer of silicon dioxide may be formed by the partial oxidation of the first silicon nitride layer. The capacitor may be a planar capacitor, may be formed in a trench, or may be formed between two layers above the surface of the substrate.

Abstract: The described embodiments of the present invention provide structures, and a method for fabricating those structures, which include a memory cell formed within a single trench. A trench is formed in the surface of a semiconductor substrate. The bottom portion of the trench is filled with polycrystalline silicon to form one plate of a storage capacitor. The substrate serves as the other plate of the capacitor. The remaining portion of the trench is then filled with an insulating material such as silicon dioxide. A pattern is then etched into the silicon dioxide which opens a portion of the sidewall and the top portion of the trench down to the polycrystalline capacitor plate. A contact is then formed between the polycrystalline capacitor plate and the substrate. Dopant atoms diffuse through the contact to form a source region on a sidewall of the trench. A gate insulator is formed by oxidation and a drain is formed at the surface of the trench adjacent to the mouth of the trench.

Abstract: A dynamic read/write memory or the like is made by a twin-well CMOS process that employs field-plate isolation rather than thick field oxide, with no separate channel stop implant. The field plate is grounded over P well areas, and connected to the positive supply over the N wells. One-transistor memory cells are of metal-gate construction with N+ drain regions buried beneath oxide, and other transistors are constructed with silicided, implanted, source/drain regions, self-aligned to the metal gates, employing sidewall oxide spacers to provide lightly-doped drains.

Abstract: A semiconductor device such as a dynamic read/write memory or the like is made by a twin-well CMOS process that employs a minimum number of photomasks. Field oxide isolation areas are formed in nitride-framed recesses so a relatively plane surface is provided, and a minimum of encroachment occurs. Both P-channel and N-channel transistors are constructed with silicided, ion-implanted, source/drain regions, self-aligned to the gates, employing an implant after sidewall oxide is in place, providing lightly-doped drains. The threshold voltages of the P-channel and N-channel transistors are established by the tank implants rather than by separate ion-implant steps for threshold adjust.

Abstract: Metal-gate transistors with metal silicide cladding of the source/drain regions, as may be used in very high density dynamic RAM devices, are made by a process in which the metal gate is encapsulated in oxide and the cladding is self aligned with the encapsulated gate. A thin coating of a refractory metal is applied to the source/drain areas and heated to react with the exposed silicon. The unreacted metal is removed by an etchant that does not disturb the metal gate or the silicide.

Abstract: An integrated circuit isolation technology wherein the nitride-sidewall methods of the prior art are improved by performing an undercut and backfill before the second nitride (the sidewall nitride which prevents encroachment) is added to the first nitride (which covers the moat areas). Thus, the butt joint between the two nitrides is made more secure, and localized bird's-beaking at the butt joint between the moat nitride and the sidewall nitride does not occur.