Abstract: A color tint controller for a closed circuit video system receives red and blue color difference signals and selectively changes the amplitudes of these signals to adjust the color of a displayed image. This is accomplished by changing the levels of the red color difference signals in a first direction, and changing the levels of the blue color difference signals in a second opposite direction, and then adding these changed signals to generate an adjusted red difference signal which is fed into a RGB matrix. At the same time, the levels of the blue difference signals are changed in the first direction and the levels of the red color difference signals are changed in the second direction, and these two signals are combined to form an adjusted blue difference signal which is also fed to the RGB matrix.

Abstract: In a skip-field video recorder, the audio signal of every field is continuously recorded. The audio signal of each skipped video field is stored in an audio field store memory and then unloaded during the recording of the next (unskipped) video field. The unloaded audio signal is multiplexed with the current incoming audio signal and recorded therewith. Alternatively, the audio signals of both the skipped field and the unskipped field may be compressed and recorded in an extended portion of each video tape track.

Abstract: A vertical synchronizing circuit wherein a counter counts pulses at twice the horizontal deflection rate and provides a vertical output pulse at a predetermined count is shown. A synchronism or mode detector causes the circuit to switch to a driven mode when the counter is not reset in synchronism with the vertical synchronizing pulses. The mode detector causes the circuit to switch to a countdown mode when synchronism is detected. A phase detector detects phase errors between the counter and the vertical synchronizing pulses when the circuit is in the countdown mode and causes the counter to delete or add counts depending upon the direction of the phase error when such phase errors persist for a predetermined number of vertical fields. The vertical synchronizing pulses are applied to a gate which is enabled in the countdown mode when the counter reaches a predetermined count shortly before a vertical synchronizing pulse is anticipated.

Abstract: A vertical synchronizing circuit wherein a counter counts pulses at twice the horizontal deflection rate and provides a vertical output pulse at a predetermined count is shown. A synchronism or mode detector causes the circuit to switch to a driven mode when the counter is not reset in synchronism with the vertical synchronizing pulses. The mode detector causes the circuit to switch to a countdown mode when synchronism is detected. A phase detector detects phase errors between the counter and the vertical synchronizing pulses when the circuit is in the countdown mode and causes the counter to delete or add counts depending upon the direction of the phase error when such phase errors persist for a predetermined number of vertical fields. The vertical synchronizing pulses are applied to a gate which is enabled in the countdown mode when the counter reaches a predetermined count shortly before a vertical synchronizing pulse is anticipated.

Abstract: A vertical synchronizing circuit wherein noise pulses or signals which may accompany vertical synchronizing pulses are locked out for a predetermined time subsequent to the receipt of a vertical synchronizing pulse is shown. A counter counts pulses at the horizontal or line deflection rate. At a particular count of the counter the vertical synchronizing circuit is conditioned for receipt of a vertical synchronizing pulse. Subsequent to the receipt of a vertical synchronizing pulse, the vertical synchronizing circuit is conditioned to be unresponsive to any received pulses until the counter again counts to the predetermined count.