Patents by Inventor Robert R. Garcia

Robert R. Garcia has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Offset geometries for area reduction in memory arrays
    Patent number: 8492205
    Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by moving adjacent similar structures that is not perpendicular to a fully identical common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: July 23, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Robert R. Garcia
  • SRAM STRAP ROW SUBSTRATE CONTACT
    Publication number: 20120300537
    Abstract: An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.
    Type: Application
    Filed: November 21, 2011
    Publication date: November 29, 2012
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Robert R. Garcia, Theodore W. Houston
  • SRAM strap row substrate contact
    Patent number: 8320165
    Abstract: An integrated circuit containing an SRAM array having a strap row. The strap row has a substrate contact structure that includes a substrate contact plug and a tap layer.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: November 27, 2012
    Assignee: Texas Instrument Incorporated
    Inventors: Robert R. Garcia, Theodore W. Houston
  • Offset geometries for area reduction in memory arrays
    Patent number: 8110855
    Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.
    Type: Grant
    Filed: July 24, 2009
    Date of Patent: February 7, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Robert R. Garcia
  • Offset Geometries for Area Reduction In Memory Arrays
    Publication number: 20110020986
    Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.
    Type: Application
    Filed: July 21, 2010
    Publication date: January 27, 2011
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Theodore W. Houston, Robert R. Garcia
  • Offset Geometries for Area Reduction in Memory Arrays
    Publication number: 20110018035
    Abstract: An array with cells that have adjacent similar structures that are displaced from each other across a common cell border in a direction that is not perpendicular to the cell border thus avoiding an across cell border design rule violation between the adjacent similar structures. A method of forming reduced area memory arrays by displacing adjacent similar structures along a common cell border. A method of building arrays using conventional array building software by forming unit pairs with cells that are not identical and are not mirror images or rotated versions of each other.
    Type: Application
    Filed: July 24, 2009
    Publication date: January 27, 2011
    Applicant: Texas Instruments Incorporated
    Inventors: Theodore W. Houston, Robert R. Garcia