Abstract: Examples described herein relate to method for measuring a disconnect response time. The method includes discontinuing, in response to a determining that a disconnect response metric test is to be initiated, transmission of a test optical signal by a test device to a DUT coupled to the test device, wherein the DUT is to discontinue transmission of a response optical signal to the test device upon detection of a loss of the test optical signal. Further, a loss of the response optical signal by may be detected by the test device. Furthermore, a disconnect response metric of the DUT may be determined by the test device based on a time of discontinuation of the transmission of the test optical signal and a time of detection of the loss of the response optical signal.

Abstract: A method for synchronizing a first processor and multiple second processors is presented. In the method, each of the second processors waits at a second synchronization point after reaching a first synchronization point. The last of the second processors to reach the first synchronization point sends a signal to the first processor. The first processor waits at the first synchronization point until it receives the signal. After receiving the signal, the first processor initiates a launch of the second processors by launching at least one of the second processors. At least one of the second processors launched by the first processor launches another of the second processors in response to being launched by the first processor. Each of the second processors continues execution from the second synchronization point in response to being launched.

Abstract: The invention includes a method of and an apparatus for testing an integrated circuit which includes simulating the integrated circuit and generating an input vector to and expected output from the integrated circuit. This input vector and expected output are generated by entering test vectors into the circuit simulator and the integrated circuit is tested using the input vector to yield a first resulting output. A test hardware vector is also created to capture state information pertaining to the integrated circuit. The test hardware vector and the input vector are combined to create a joint input vector and debugging is performed on the integrated circuit by modifying the joint input vector and evaluating the resulting output.

Abstract: The invention includes a method of and an apparatus for testing an integrated circuit which includes simulating the integrated circuit and generating an input vector to and expected output from the integrated circuit. This input vector and expected output are generated by entering test vectors into the circuit simulator and the integrated circuit is tested using the input vector to yield a first resulting output. A test hardware vector is also created to capture state information pertaining to the integrated circuit. The test hardware vector and the input vector are combined to create a joint input vector and debugging is performed on the integrated circuit by modifying the joint input vector and evaluating the resulting output.