Patents by Inventor Robert R. Roeder

Robert R. Roeder has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • No-touch stress testing of memory I/O interfaces
    Patent number: 8924786
    Abstract: Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: December 30, 2014
    Assignee: Intel Corporation
    Inventors: Sankaran M. Menon, Robert R. Roeder
  • Method and apparatus for testing I/O boundary scan chain for SoC's having I/O's powered off by default
    Patent number: 8904253
    Abstract: Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: December 2, 2014
    Assignee: Intel Corporation
    Inventors: Sankaran M. Menon, Robert R. Roeder, Liwei E. Ju
  • NO-TOUCH STRESS TESTING OF MEMORY I/O INTERFACES
    Publication number: 20140006864
    Abstract: Embodiments are generally directed no-touch stress testing of memory input/output (I/O) interfaces. An embodiment of a memory device includes a system element to be coupled with a dynamic random-access memory (DRAM), the system element including a memory interface for connection with the DRAM, the interface including a driver and a receiver, a memory controller for control of the DRAM, and a timing stress testing logic for testing of the I/O interface.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: Intel Corporation
    Inventors: Sankaran M. Menon, Robert R. Roeder
  • METHOD AND APPARATUS FOR TESTING I/O BOUNDARY SCAN CHAIN FOR SOC'S HAVING I/O'S POWERED OFF BY DEFAULT
    Publication number: 20130346816
    Abstract: Methods and apparatus for testing Input/Output (I/O) boundary scan chains for Systems on a Chip (SoCs) having I/Os that are powered off by default. Some methods and apparatus include implementation of boundary scan chain bypass routing schemes that selectively route a boundary scan chain path around I/O interfaces and/or ports that are powered off by default. Other techniques include selectively power-on I/Os that are powered off by default in a manner that is independent of SoC facilities for controlling the power state of the I/Os during SoC runtime operations. Various schemes facilitate boundary scan testing in accordance with IEEE Std.-1149.1 methodology.
    Type: Application
    Filed: June 25, 2012
    Publication date: December 26, 2013
    Inventors: Sankaran M. Menon, Robert R. Roeder, Liwei E. Ju