Abstract: The data cache management mechanism of the present invention is created by an optimizing compiler. The optimizing compiler intelligently places non-blocking preload instructions into the instruction stream of the computer system so as to minimize both the frequency and detrimental effect of cache misses. The non-blocking preload instructions are placed into the instruction stream based on the existence of predictor constructs that foretell what information the processor will need and when it will need it. As a result, cache misses are either avoided entirely or reduced in severity.