Abstract: An intermedullary device and methods of use are described. The device is configured for fixation of a long bone and to facilitate healing of the long bone. The device comprises an elongate member having a first end, a second end, and a mid region. The mid region comprises a band or collar extending outwardly away from the outer surface of the device to increase all or a portion of the cross-sectional diameter of the mid region. The elongate member has a length that may be about the same as or less than the length of the long bone's diaphyseal region. The band further comprises at least one engaging surface configured for engaging with a cortical region of the long bone at a defect site. Use of the device facilitates healing of the long bone at or near the defect site. The method comprises providing a first end of the device in a first exposed region of the long bone's medullary canal. The method further comprises providing a second end of the device in a second exposed region of the medullary canal.

Abstract: A method, apparatus, and computer instructions for managing a set of signal paths for a chip. A defective signal path within the set of signal paths for the chip is detected. Signals are re-routed through the set of signal paths such that the defective signal path is removed from the set of signal paths and sending signals using remaining data signal paths in the set of signal paths and using an extra signal path in response to detecting the defective signal path.

Abstract: A method of entropy encoding image or video data may include entropy encoding a number of blocks independently and in parallel to generate a number of bit streams. At least one of the number of bit streams may include an assumed value in place of a value that would be determined by another bit stream. The method may also include selectively correcting the assumed value based on a value in another one of the number of bit streams. The number of bit streams may be combined into an output, entropy encoded bit stream corresponding to the number of blocks.

Abstract: An interface alignment pattern for de-skewing data bits received on an elastic interface is disclosed. The interface alignment pattern is “busy” in that it has a high number of logic state transitions. The busy interface alignment pattern can be used for scrambling and unscrambling operational data. The interface alignment pattern has a unique timing sequence for determining the location of a data bit's first data beat.

Abstract: Methods, systems, and media for functional simulation of an I/O bus are disclosed. More particularly, a method of simulating distortion and noise parameters of an I/O bus is disclosed. Embodiments include constraining one or more fields of a record and determining delay amounts based on the resulting parameters, where the final delay amount includes a delay buffer and a net of delay amounts associated with the parameters. Embodiments may also include determining a value of a next bit to be sent to the I/O bus and, after waiting the delay amount, driving the bit on the bus to the next bit value. Parameters may include skew, jitter, duty cycle distortion, voltage reference distortion, and drift of any of these parameters. Further embodiments may include signaling the end of a phase in response to a phase done condition being satisfied.

Abstract: A method and apparatus for de-skewing and aligning digital data received over and elastic interface bus is disclosed. Upon receiving the data, it is sent through a programmable delay line. While in the programmable delay line, the data is sampled at three points within the data's eye pattern. The three sampling points are dynamically adjusted to maximize coverage of the data's eye pattern. During the adjustment of the sampling points to optimally cover the data's eye pattern, delayed data is sampled from an alternate sampler to prevent sampling from the functional sampler while the delay in the primary sampler is adjusted. Sampling from the alternate sampler while changing the sampling points of the functional sampler serves to reduce glitches that may occur by sampling the functional sampler while its sampling parameters are changed. The method and apparatus allow for alternate eye tracking and wraparound eye tracking.

Abstract: Methods and apparatus are disclosed for aligning received data bits in elastic interface systems. Depending upon which one of several alignment modes is selected, data bits can be loaded into FIFO latches on rising clock edges if the data was sent on rising clock edges, on falling clock edges if the data was sent on falling clock edges, or on the nearest clock edge if minimum latency is desired. Alternatively, data bits can be delayed by one or more bit times before loading into FIFO latches to reduce the elastic interface system's sensitivity to drift. The present invention permits a user to trade off factors related to for latency, drift, and skew by choosing among different alignment modes in an elastic interface system.

Abstract: Pseudo-differential drivers and receivers are used to communicate data signals between two or more IC chips. The data paths are aligned using programmable delay circuitry to de-skew each data path. A programmable reference generator is used to generate a reference voltage used by one or a group of receivers to detect the data signals. The reference voltage is adjustable using coarse as well as fine digitally controlled voltage increments. Test signals are sent from the driver to the receiver and the reference voltage is varied over its adjustable range using the coarse and fine adjustment controls while circuitry determines a measure of the detection timing jitter on successive transitions of the test signal. The operational value of the reference voltage is set to the value where the detection timing jitter is determined to be a minimum.

Abstract: Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges and the asymmetry in a compensated clock signal detected from the differential clock using a duty cycle adjustment circuit. Error detection determines if the clock asymmetry is affecting the eye window of the data signals. Control signals selectively adjust the gain of differential stages generating the compensated clock to modify the duty cycle of the compensated clock. The eye window of the data signals are monitored and used as feedback to servo the control signals to optimize the duty cycle of the compensated clock signal for sampling the data signals.

Abstract: A test pattern is loaded into a driver data shift register and sent from a driver chip to a receive chip over an M bit bus (0 to M?1). The test pattern is also generated at the receiver chip and used to compare to the actual received data. Failed compares are stored as logic ones in a bit error register (BER). A counter determines the number of failures by counting logic ones from the BER. The contents of a error position counter are latched in a error position latch and used to load a logic one (at the error bit position) into daisy chained self-heal control registers (SCR) in the receiver chip and the driver chip. The SCR sets a logic one into all bit positions after the error bit isolating the failed bit path and adding a spare bit path which is in bit position M.

Abstract: A mechanism for de-skewing and aligning data bits sent between two chips on an elastic interface. On the receiving end of an elastic interface, the eye of each data bit within a clock/data group is delayed by less than a bit time to align the eyes with the nearest clock edge of a received clock signal. In addition to aligning the eyes of the individual data bits with the nearest clock edge, IAP patterns are used to determine the amount of further delay needed to line up the individual data beats from each data bit. If the data beats for the data bits are not aligned, all but the slowest data beat are delayed to align the data beats for all bits. The additional delay is achieved using sample latches that result in a delayed signal with less jitter. As a result of having less jitter, the received, de-skewed, and aligned clock/data group can be forwarded to the operative portion of the receiving chip at an increased frequency.

Abstract: A power supply voltage insensitive delay element is provided that enables a digital signal to be delayed without variation due to power supply vulnerabilities. Current is limited through the transistors of the delay element using bias voltages produced by a bias voltage generator coupled to the delay element. The bias voltage generator and the delay element are included in a delay line which facilitates the providing of a delay that is insensitive to voltage fluctuations.

Abstract: A method for evaluating an end-user's subjective assessment of streaming media quality includes obtaining reference data characterizing the media stream, and obtaining altered data characterizing the media stream after the media stream has traversed a channel that includes a network. An objective measure of the QOS of the media stream is then determined by comparing the reference data and the altered data.

Abstract: Identifying content and authorizing sharing thereof based at least in part on extracting feature data from content to be shared and comparing this extracted feature data against a database of extracted feature data for various reference content. When the content to be shared is matched to reference content in the database, sharing may be simply rejected, or rights associated with the reference content may be inspected to facilitate determining authorization.

Abstract: Circuitry used to de-skew data channels coupling parallel data signals over a communication link employs SOI circuitry that is subject to generating pulse distortion due to the history effect modifying threshold voltages. To substantially eliminate the pulse distortion, data signals are XOR with a repeating scramble data pattern that generates scrambled data with a minimum average ratio of logic ones to logic zeros logic zeros to logic ones. The scrambled data is sent over the communication link and de-skewed in the SOI circuitry with little or no pulse distortion. The scramble data pattern is again generated at the receiver side of the communication link after a delay time to synchronize the logic states of the scramble data pattern that generated the scrambled data with the scrambled data at the receiver side. The delayed scrambled data pattern is again XOR'ed with the scrambled data to recover the data signal.

Abstract: Techniques for image edge filter processing are provided. Data samples surrounding vertical and horizontal edges of an image are acquired and iteratively processed. If the samples are associated with vertical edges, the data associated with the samples are transposed prior to applying a selected filter. The samples are stored in two buffers (one buffer for each unique side of an edge being processed) and selective filters applied thereon. Each sample set includes more than four samples of data. Once the filters are processed, the data in the buffers is written as portions of a modified image. If the samples were associated with vertical edges, then the data is re-transposed out of the buffers as it is written.

Abstract: A refrigerated cold beverage merchandiser (10) includes an enclosure defining an insulated, refrigerated display cabinet (25) and a compartment (30) heat insulated therefrom wherein a compressor (40) a condenser (50) and a condenser fan (60) are disposed. The condenser (50) is formed by a plurality of in-line tube banks (52). Each tube bank (52) is a serpentine tube formed a plurality of unfinned, straight tube segments (54) extending in parallel rows (55) between a pair of spaced, opposed end plates (58) and elbow turns (56) connecting neighboring straight tube segments (56) in a conventional manner. Each successive tube bank (52) is arranged with the other tube banks so that respective parallel tube rows (55) are disposed in-line from the front to the rear of the condenser (50) or with each successive tube bank being offset in a slightly staggered arrangement.

Abstract: A refrigerated cold beverage merchandiser (10) includes an enclosure defining an insulated, refrigerated display cabinet (25) and a compartment (30) heat insulated therefrom wherein a compressor (40) a condenser (50) and a condenser fan (60) are disposed. The condenser (50) is formed by a plurality of in-line tube banks (52). Each tube bank (52) is a serpentine tube formed a plurality of unfinned, straight tube segments (54) extending in parallel rows (55) between a pair of spaced, opposed end plates (58) and elbow turns (56) connecting neighboring straight tube segments (56) in a conventional manner. Each successive tube bank (52) is arranged with the other tube banks so that respective parallel tube rows (55) are disposed in-line from the front to the rear of the condenser (50) or with each successive tube bank being offset in a slightly staggered arrangement.

Abstract: A refrigerated cold beverage merchandiser (10) includes an enclosure defining an insulated, refrigerated display cabinet (25) and a compartment (30) heat insulated therefrom wherein a compressor (40) a condenser (50) and a condenser fan (60) are disposed. The condenser (50) is formed by a plurality of in-line tube banks (52). Each tube bank (52) is a serpentine tube formed a plurality of unfinned, straight tube segments (54) extending in parallel rows (55) between a pair of spaced, opposed end plates (58) and elbow turns (56) connecting neighboring straight tube segments (56) in a conventional manner. Each successive tube bank (52) is arranged with the other tube banks so that respective parallel tube rows (55) are disposed in-line from the front to the rear of the condenser (50) or with each successive tube bank being offset in a slightly staggered arrangement.

Abstract: A method and apparatus for decoding a bitstream.