Patents by Inventor Robert Ringel

Robert Ringel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8185226
    Abstract: By defining a section-related WIP limit or a throughput-related WIP limit, an efficient “look ahead” characteristic may be established to efficiently control the WIP in a complex manufacturing environment, such as a semiconductor facility. The respective critical WIP values may enable efficient reduction of priority of products moving towards an increased WIP queue, thereby reducing or substantially avoiding the release of products that are expected to run into the WIP queue. In this way, the efficiency of shared tools may be increased, since process capacity no longer required for the processing products running into WIP queues may be allocated for other operations.
    Type: Grant
    Filed: May 12, 2008
    Date of Patent: May 22, 2012
    Assignee: Globalfoundries Inc.
    Inventors: Joerg Weigang, Robert Ringel, Steffen Kalisch, Thomas Quarg
  • Patent number: 7908127
    Abstract: By simulating a manufacturing environment on the basis of appropriate simulation models, a schedule may be established in which process restrictions, tool availability and product entity status are automatically taken into consideration. Moreover, by estimating the process flow efficiency provided by a simulated time progression of the process flow in the environment, an optimized schedule may be established, which may be accomplished by identifying less efficient product entities and re-scheduling one or more product entities in order to obtain an enhanced process flow efficiency. The technique of the present invention may be advantageously applied to the processing of advanced mass products requiring sophisticated process tools and process sequences, such as the processing of semiconductor devices.
    Type: Grant
    Filed: October 4, 2006
    Date of Patent: March 15, 2011
    Assignee: GlobalFoundries, Inc.
    Inventors: Joerg Weigang, Robert Ringel, Arndt Herrmann
  • Publication number: 20090037012
    Abstract: By defining a section-related WIP limit or a throughput-related WIP limit, an efficient “look ahead” characteristic may be established to efficiently control the WIP in a complex manufacturing environment, such as a semiconductor facility. The respective critical WIP values may enable efficient reduction of priority of products moving towards an increased WIP queue, thereby reducing or substantially avoiding the release of products that are expected to run into the WIP queue. In this way, the efficiency of shared tools may be increased, since process capacity no longer required for the processing products running into WIP queues may be allocated for other operations.
    Type: Application
    Filed: May 12, 2008
    Publication date: February 5, 2009
    Inventors: Joerg Weigang, Robert Ringel, Steffen Kalisch, Thomas Quarg
  • Publication number: 20070179652
    Abstract: By simulating a manufacturing environment on the basis of appropriate simulation models, a schedule may be established in which process restrictions, tool availability and product entity status are automatically taken into consideration. Moreover, by estimating the process flow efficiency provided by a simulated time progression of the process flow in the environment, an optimized schedule may be established, which may be accomplished by identifying less efficient product entities and re-scheduling one or more product entities in order to obtain an enhanced process flow efficiency. The technique of the present invention may be advantageously applied to the processing of advanced mass products requiring sophisticated process tools and process sequences, such as the processing of semiconductor devices.
    Type: Application
    Filed: October 4, 2006
    Publication date: August 2, 2007
    Inventors: Joerg Weigang, Robert Ringel, Arndt Herrmann