Abstract: A method of allocating space in a frame buffer memory which is not used for storing pixels to be displayed currently including the steps of selecting a portion of the memory to be allocated for off-screen memory; determining the size of an area to be allocated; comparing the size of the area to be allocated with portions of the memory available to be allocated for off-screen memory using a memory allocation technique in which the least area considered is at least as great in either its horizontal or its vertical dimension as the greater dimension of the area to be allocated, the comparison being conducted in a pattern which consistently checks first a minimum area followed by three other minimum areas in an area having a size which is the next power of two larger in each dimension than the minimum area, then four more minimum areas in an adjacent area having a size which is the next power of two larger in each dimension than the minimum area than the minimum area in the pattern, the area selected for the seco

Abstract: A predictive caching system for use in computer system having at least one portion of memory in which information is stored for retrieval, a general cache used to speed the operation of accessing such memory, and a processor for controlling the access of the memory comprising apparatus for discerning a pattern of access of the memory, apparatus operating in response to the pattern determined by the apparatus for discerning a pattern of access of the memory for determining a next address which will probably accessed in such memory if the pattern discerned continues, and apparatus for storing the information at the next address determined prior to the next access of the memory whereby the information at the next address is available without the need to access the memory.

Abstract: A method for manipulating graphic images using a computer system in which each graphic image is broken into a series of rectangles and the individual rectangles of one graphic image are combined with the individual rectangles of another graphic image to form a shape data structure which may be stored and utilized for purposes of graphic display.

Abstract: A method for allowing direct graphics access to backup storage areas in frame buffer memory used for retained windows and controlled by a graphics accelerator which includes the steps of establishing a shared memory file in system memory for the backup storage area indicating that the retained windows area initially exists in excess frame buffer memory, the shared memory file having storage to indicate the use of the shared area by a process; generating a page fault whenever access to the graphics accelerator is attempted and the state of another process is stored on the graphics accelerator; and calling a device driver in response to the page fault to switch the context stored on the graphics accelerator to that of the process attempting the access.

Abstract: A method of initiating a write operation for a particular command from a first computer module through a system interface to a second computer module having data registers, and a status register which includes the steps of writing data to the data registers in the second computer module, and determining the status of the status register in the second computer module to cause the initiation of the particular command by which the reading the status of the data registers and issuing the particular command as separate steps are eliminated.

Abstract: The system of the present invention provides for the context switching of devices connected through the system's memory management unit and is particularly useful in a multi-tasking computer system in which multiple processes access the same device. In the method and apparatus of the present invention, devices that are connected to the system through the MMU are controlled using the page fault mechanism of the MMU and the page fault handler in each segment. Addresses are allocated in the process address space for each process to provide for the addressing of the devices and device queues connected through the MMU, such that one device or one device queue is mapped into one segment of each process address space that will access the device. The "valid bits" associated with each page in a segment are turned on/off by the process or operating system in order to control the device.