Patents by Inventor Robert Rogenmoser

Robert Rogenmoser has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9966130
    Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
    Type: Grant
    Filed: June 27, 2017
    Date of Patent: May 8, 2018
    Assignee: MIE Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Publication number: 20170301395
    Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
    Type: Application
    Filed: June 27, 2017
    Publication date: October 19, 2017
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Patent number: 9741428
    Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: August 22, 2017
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Publication number: 20160232964
    Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 11, 2016
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Patent number: 9362291
    Abstract: An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-gate transistors having a screening region a distance below the gate and separated from the gate by a semiconductor layer, the screening region having a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer, the screening region providing an enhanced body coefficient for the pull-down transistors and the pass-gate transistors to increase the read static noise margin for the SRAM cell when a bias voltage is applied to the screening region; and a bias voltage network operable to apply one or more bias voltages to the multiple SRAM cells.
    Type: Grant
    Filed: August 9, 2014
    Date of Patent: June 7, 2016
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Patent number: 9154123
    Abstract: An integrated circuit can include a plurality of drive monitoring sections, each including at least one transistor under test (TUT) having a source coupled to a first power supply node, a gate coupled to receive a start indication, and a drain coupled to a monitor node, at least one monitor capacitor coupled to the monitor node, and a timing circuit configured to generate a monitor value corresponding to a rate at which the TUT can transfer current between the monitor node and the first power supply node; and a body bias circuit configured to apply a body bias voltage to at least one body region in which at least one transistor is formed; wherein the body bias voltage is generated in response to at least a plurality of the monitor values.
    Type: Grant
    Filed: August 19, 2014
    Date of Patent: October 6, 2015
    Assignee: Mie Fujitsu Semiconductor Limited
    Inventors: Lawrence T. Clark, Michael S. McGregor, Robert Rogenmoser, David A. Kidd, Augustine Kuo
  • Patent number: 8995204
    Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: March 31, 2015
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Bruce McWilliams, Robert Rogenmoser
  • Patent number: 8970289
    Abstract: An integrated circuit device can include at least a first bi-directional biasing circuit having a first substrate portion containing a plurality of first transistors; a first control digital-to-analog converter (DAC) to generate any of a plurality of first target values in response to a first target code; a first detect circuit configured to generate a difference value between the first target values and a first limit value; and at least a first charge pump circuit configured to drive the first substrate portion between a forward body bias voltage and a reverse body bias voltage for the first transistors in response to first target values. Embodiments can also include a performance monitor section configured to determine a difference between the voltage of the first substrate portion and a target voltage. Control logic can generate first code values in response to the difference between the voltage of the first substrate portion and the target voltage. Methods are also disclosed.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: March 3, 2015
    Assignee: Suvolta, Inc.
    Inventors: Sang-Soo Lee, Edward J. Boling, Augustine Kuo, Robert Rogenmoser
  • Patent number: 8816754
    Abstract: An integrated circuit can include an operational section comprising a first body bias circuit coupled to drive first body regions to a first bias voltage in response to at least first bias values; a second body bias circuit coupled to drive second body regions to a second bias voltage in response to at least second bias values; a plurality of monitoring sections formed in a same substrate as the operational section, each configured to output a monitor value reflecting a different process variation effect on circuit performance.
    Type: Grant
    Filed: November 2, 2012
    Date of Patent: August 26, 2014
    Assignee: SuVolta, Inc.
    Inventors: Lawrence T. Clark, Michael S. McGregor, Robert Rogenmoser, David A. Kidd, Augustine Kuo
  • Patent number: 8811068
    Abstract: An integrated circuit can include SRAM cells, with pull-up transistors, pull-down transistors, and pass-gate transistors having a screening region positioned a distance below the gate and separated from the gate by a semiconductor layer. The screening region has a concentration of screening region dopants, the concentration of screening region dopants being higher than a concentration of dopants in the semiconductor layer. The screening region can provide an enhanced body coefficient for the pull-up transistors to increase a read static noise margin of the SRAM cell when a bias voltage is applied to the screening region. Related methods are also disclosed.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: August 19, 2014
    Assignee: Suvolta, Inc.
    Inventors: Lawrence T. Clark, Scott E. Thompson, Richard S. Roy, Robert Rogenmoser, Damodar R. Thummalapally
  • Publication number: 20120327725
    Abstract: Circuits, integrated circuits devices, and methods are disclosed that may include biasable transistors with screening regions positioned below a gate and separated from the gate by a semiconductor layer. Bias voltages can be applied to such screening regions to optimize multiple performance features, such as speed and current leakage. Particular embodiments can include biased sections coupled between a high power supply voltage and a low power supply voltage, each having biasable transistors. One or more generation circuits can generate multiple bias voltages. A bias control section can couple one of the different bias voltages to screening regions of biasable transistors to provide a minimum speed and lowest current leakage for such a minimum speed.
    Type: Application
    Filed: June 23, 2011
    Publication date: December 27, 2012
    Applicant: SUVOLTA, INC.
    Inventors: Lawrence T. Clark, Bruce McWilliams, Robert Rogenmoser
  • Patent number: 7269714
    Abstract: A processor is described which includes a first pipeline, a second pipeline, and a control circuit. The first pipeline includes a first stage at which instruction results are committed to architected state. The first stage is separated from an issue stage of the first pipeline by a first number of stages. The second pipeline includes a second stage at which an exception is reportable, wherein the second stage is separated from the issue stage of the second pipeline by a second number of stages which is greater than the first number. The control circuit is configured to inhibit co-issuance of a first instruction to the first pipeline and a second instruction to the second pipeline if the first instruction is subsequent to the second instruction in program order.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: September 11, 2007
    Assignee: Broadcom Corporation
    Inventors: Tse-Yu Yeh, David A. Kruckemyer, Robert Rogenmoser
  • Patent number: 7100064
    Abstract: An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: August 29, 2006
    Assignee: Broadcom Corporation
    Inventors: Robert Rogenmoser, Michael C. Kim, Tse-Yu Yeh
  • Patent number: 6995600
    Abstract: An apparatus for a multiplexor circuit includes a passgate circuit coupled to receive input signals and corresponding select signals comprising a subset of the input signals and select signals received by the multiplexor. The apparatus also includes a default circuit coupled to receive the select signals and coupled to an output node of the passgate circuit. If none of the select signals is asserted, the default circuit supplies a default voltage on the output node. Other passgate circuits and default circuits may be included coupled to other subsets of the input signals and select signals, and an output circuit may be included with inputs coupled to the output nodes of the passgate circuits. The default voltage may represent a logical value which allows the value from another passgate circuit to control the output of the output circuit.
    Type: Grant
    Filed: July 9, 2001
    Date of Patent: February 7, 2006
    Assignee: Broadcom Corporation
    Inventors: Robert Rogenmoser, Lief O'Donnell
  • Patent number: 6988115
    Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.
    Type: Grant
    Filed: May 4, 2001
    Date of Patent: January 17, 2006
    Assignee: Broadcom Corporation
    Inventors: Robert Rogenmoser, Lief O'Donnell
  • Patent number: 6976152
    Abstract: An apparatus for a processor includes a first scoreboard, a second scoreboard, and a control circuit coupled to the first scoreboard and the second scoreboard. The control circuit is configured to update the first scoreboard to indicate that a write is pending for a first destination register of a first instruction in response to issuing the first instruction into a first pipeline. The control circuit is configured to update the second scoreboard to indicate that the write is pending for the first destination register in response to the first instruction passing a first stage of the pipeline. Replay may be signaled for a given instruction at the first stage. In response to a replay of a second instruction, the control circuit is configured to copy a contents of the second scoreboard to the first scoreboard. In various embodiments, additional scoreboards may be used for detecting different types of dependencies.
    Type: Grant
    Filed: February 4, 2002
    Date of Patent: December 13, 2005
    Assignee: Broadcom Corporation
    Inventors: Tse-Yu Yeh, David A. Kruckemyer, Randel P. Blake-Campos, Robert Rogenmoser, Robert Stepanian
  • Publication number: 20050223055
    Abstract: A leading one correction circuit receives a significand from a floating point adder and a corresponding leading one prediction from a leading one predictor, and determines if the leading one prediction is correct. In one embodiment, the leading one prediction is a one hot vector having the same number of bits as the significand, with the set bit in the position predicted to have the leading one. In such an embodiment, the leading one correction circuit may perform a bitwise AND of the significand and leading one prediction, and the result of the bitwise AND may be ORed to generate a signal indicating whether or not the prediction is correct. In one implementation, the leading one correction circuit may operate concurrent with a shift of the significand in response to a shift amount indicated by the leading one prediction.
    Type: Application
    Filed: June 7, 2005
    Publication date: October 6, 2005
    Inventors: Robert Rogenmoser, Lief O'Donnell
  • Patent number: 6941334
    Abstract: A floating point unit includes a multiplier, an approximation circuit, and a control circuit coupled to the multiplier and the approximation circuit. The approximation circuit is configured to generate an approximation of a difference of the first result from the multiplier and a constant. The control circuit is configured to approximate a function specified by a floating point instruction provided to the floating point unit for execution using an approximation algorithm. The approximation algorithm comprises at least two iterations through the multiplier and optionally the approximation circuit. The control circuit is configured to correct the approximation from the approximation circuit from a first iteration of the approximation algorithm during a second iteration of the approximation algorithm by supplying a correction vector to the multiplier during the second iteration. The multiplier is configured to incorporate the correction vector into the first result during the second iteration.
    Type: Grant
    Filed: February 1, 2002
    Date of Patent: September 6, 2005
    Assignee: Broadcom Corporation
    Inventors: Robert Rogenmoser, Michael C. Kim
  • Patent number: 6671216
    Abstract: A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.
    Type: Grant
    Filed: January 22, 2003
    Date of Patent: December 30, 2003
    Assignee: Broadcom Corporation
    Inventors: Robert Rogenmoser, Steve T. Nishimoto, Daniel W. Dobberpuhl
  • Publication number: 20030225999
    Abstract: An integrated circuit includes at least a first fuse and at least a first processor. Each fuse is in either a conductive state or a non-conductive state. The first processor is configured to operate at one of at least a first issue rate or a second issue rate responsive to the state of the first fuse. The first issue rate is lower than the second issue rate. In another embodiment, the first processor is configured to execute fewer instructions in a period of time responsive to a first state of the conductive state or the non-conductive state of the first fuse than the first processor is configured to execute in the period of time responsive to a second state of the first fuse. A method includes: (i) determining if an integrated circuit comprising at least one processor has a performance rating that exceeds a government-imposed export restriction; and (ii) in response to the performance rating exceeding the export restriction, blowing at least one fuse on the integrated circuit.
    Type: Application
    Filed: May 30, 2002
    Publication date: December 4, 2003
    Inventors: Robert Rogenmoser, Michael C. Kim, Tse-Yu Yeh