Abstract: Glass separation systems for separating glass substrates from a continuous glass ribbon are disclosed. In one embodiment, the system may include an A-surface nosing bar positioned on a first side of a glass conveyance pathway. A long axis of the A-surface nosing bar may be substantially orthogonal to a conveyance direction of the glass conveyance pathway. The glass separation system may further comprise a B-surface nosing bar positioned on a second side of the glass conveyance pathway and opposite the A-surface nosing bar. A long axis of the B-surface nosing bar may be substantially orthogonal to the conveyance direction of the glass conveyance pathway. The A-surface nosing bar and the B-surface nosing bar may be pivotable about axes of rotation parallel to the conveyance direction of the glass conveyance pathway.

Abstract: Disclosed are various embodiments for evaluating an application under development through use of a viewer application executing in a computer. The computer retrieves an application package comprising code for a target application to be evaluated in the computer. The code for the target application is stored in a memory of the computer accessible to the viewer application. The code for the target application is stored without installing the target application as a stand-alone application on the computer. Code of the viewer application is executed in order to execute the stored code for the target application for evaluation. Executing the stored code of the target application executes the target application within the execution of the viewer application.

Abstract: Disclosed are various embodiments for evaluating an application under development through use of a viewer application executing in a computer. The computer retrieves an application package comprising code for a target application to be evaluated in the computer. The code for the target application is stored in a memory of the computer accessible to the viewer application. The code for the target application is stored without installing the target application as a stand-alone application on the computer. Code of the viewer application is executed in order to execute the stored code for the target application for evaluation. Executing the stored code of the target application executes the target application within the execution of the viewer application.

Abstract: The present invention is directed to systems and methods of creating and deploying electronic forms for collecting information from a user using a browser, where the browser may be one of a plurality of browser platforms. Characteristics of forms are entered by a human designer using a form designer by using drag-and-drop operations, and stored in XML template files. The form may be previewed by the designer. When a user on the Internet (or an intranet) requests a form by a browser, the characteristics of the browser are sensed and a form appropriate for the browser is deployed to the browser by a form server. Information is then captured from the user. The form may also be saved or printed.

Abstract: A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Abstract: A method is described for converting an existing die, originally designed for a non-chip-scale package, to a chip-scale package die, where the die's bonding pads are located in positions within a defined grid of candidate positions. In the first step, the die's layout, comprising its outer boundaries and areas needed to be electrically connected to bonding pads, are shifted relative to a grid of candidate positions for the bonding pads until an optimal alignment is identified. Bonding pads positions on the die are then selected corresponding to optimum grid positions within the outer boundaries of the die. The die is then fabricated using the original masks to form at least the semiconductor regions and using a new set of masks for defining the new locations of the bonding pads for the chip-scale package. The chip-scale package is then bonded to a PCB using chip-scale package technology.

Abstract: The present invention is directed to systems and methods of creating and deploying electronic forms for collecting information from a user using a browser, where the browser may be one of a plurality of browser platforms. Characteristics of forms are entered by a human designer using a form designer by using drag-and-drop operations, and stored in XML template files. The form may be previewed by the designer. When a user on the Internet (or an intranet) requests a form by a browser, the characteristics of the browser are sensed and a form appropriate for the browser is deployed to the browser by a form server. Information is then captured from the user. The form may also be saved or printed.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Abstract: A lithographic pattern includes a first scribe along an edge of a die region, and a second scribe along an opposing edge of the die region. The first scribe includes at least a first translucent box and a second translucent box. The second scribe includes at least a first opaque box and a second opaque box defined respectively by a first translucent frame and a second translucent frame. When the lithographic pattern is stepped between fields on a wafer, the first translucent box is placed at least partially within the first opaque box, and the second translucent box is placed at least partially within the second opaque box. If a continuous ring is formed from a pair of a translucent box and an opaque box, the fields are aligned at least within an amount equal to the difference between the dimensions of that translucent box and that opaque box divided by 2.

Abstract: Wafer-level chip-scale packaging technology is used for improving performance or reducing size of integrated circuits by using metallization of pad-to-bump-out beams as part of the integrated circuit structure. Chip-scale packaging under bump metal is routed to increase the thickness of top metal of the integrated circuit, increasing current carrying capability and reducing resistance. An exemplary embodiment for a power MOSFET array integrated structure is described. Another exemplary embodiment illustrated the use of chip-scale processes for interconnecting discrete integrated circuits.

Abstract: The present invention is directed to systems and methods of creating and deploying electronic forms for collecting information from a user using a browser, where the browser may be one of a plurality of browser platforms. Characteristics of forms are entered by a human designer using a form designer by using drag-and-drop operations, and stored in XML template files. The form may be previewed by the designer. When a user on the Internet (or an intranet) requests a form by a browser, the characteristics of the browser are sensed and a form appropriate for the browser is deployed to the browser by a form server. Information is then captured from the user. The form may also be saved or printed.