Abstract: A CMOS power saving comparator/inverter circuit includes a complementary differential amplifier, one input of which is coupled to a voltage input. Another input of the complementary differential amplifier is coupled to a voltage reference circuit which includes two relatively high value resistors coupled in series between a P-channel MOSFET coupled to the positive voltage conductor and N-channel MOSFET coupled to the ground voltage conductor. An output of the differential amplifier is connected to an input of a CMOS inverter having its output connected to an output of the comparator/inverter circuit. The transition point, defined as the value of input voltage at which the output voltage is equal to one-half of the supply voltage, is virtually independent of the P-channel and N-channel threshold voltages. The transition point is much sharper than the transition point for a conventional CMOS inverter, and much less dependent upon various manufacturing parameter variations.

Abstract: A multi-state CMOS synchronous binary counter is implemented utilizing a CMOS transmission gate look-ahead carry circuit requiring only a fraction of the area required for AND or NAND gate carry structures.