Patents by Inventor Robert S. Chappell

Robert S. Chappell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9069690
    Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: June 30, 2015
    Assignee: Intel Corporation
    Inventors: Gur Hildesheim, Chang Kian Tan, Robert S. Chappell, Rohit Bhatia
  • Publication number: 20150089186
    Abstract: A processing device implementing store address prediction for memory disambiguation in a processing device is disclosed. A processing device of the disclosure includes a store address predictor to predict an address for store operations that store data to a memory hierarchy. The processing device further includes a store buffer for buffering the store operations prior to completion, the store buffer to comprise the predicted address for each of the store operations. The processing device further includes a load buffer to buffer a load operation, the load operation to reference the store buffer to, based on the predicted addresses, determine whether to speculatively execute ahead of each store operation and to determine whether to speculatively forward data from one of the store operations.
    Type: Application
    Filed: September 25, 2013
    Publication date: March 26, 2015
    Inventors: Ho-Seop Kim, Robert S. Chappell, Choon Y. Soo, Srikanth T. Srinivasan
  • Publication number: 20150032998
    Abstract: An apparatus and method is described herein for providing speculation control instructions. An xAcquire and xRelease instruction are provided to define a critical section. In one embodiment, the xAcquire instruction includes a lock instruction with an elision prefix and the xRelease instruction includes a lock release instruction with an elision prefix. As a result, a processor is able to elide locks and transactionally execute a critical section defined in software by xAcquire and xRelease. But by adding only prefix hints, legacy processor are able to execute the same code by just ignoring the hints and executing the critical section traditionally with locks to guarantee mutual exclusion. Moreover, xBegin and xEnd are similarly provided for in an Instruction Set Architecture (ISA) to define a transactional code region.
    Type: Application
    Filed: February 2, 2012
    Publication date: January 29, 2015
    Inventors: Ravi Rajwar, Martin G. Dixon, Konrad K. Lai, Alexandre J. Farcy, Bret L. Toll, Robert S. Chappell, Matthew C. Merten, Rajesh S. Parthasarathy, Per Hammarlund
  • Publication number: 20150006834
    Abstract: An apparatus and method are described for store durability and ordering in a persistent memory architecture. For example, one embodiment of a method comprises: performing at least one store operation to one or more addresses identifying at least one persistent memory device, the store operations causing one or more memory controllers to store data in the at least one persistent memory device; sending a request message to the one or more memory controllers instructing the memory controllers to confirm that the store operations are successfully committed to the at least one persistent memory device; ensuring at the one or more memory controllers that at least all pending store operations received at the time of the request message will be committed to the persistent memory device; and sending a response message from the one or more memory controllers indicating that the store operations are successfully committed to the persistent memory device.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 1, 2015
    Inventors: Subramanya R. DULLOOR, Sanjay KUMAR, Rajesh M. SANKARAN, Gilbert NEIGER, Richard A. UHLIG, Robert S. CHAPPELL, Joseph NUZMAN, Kai CHENG, Sailesh KOTTAPALLI, Yen-Cheng LIU, Mohan KUMAR, Raj K. RAMANUJAN, Glenn J. HINTON
  • Publication number: 20150006452
    Abstract: An apparatus and method for store dependence prediction is described. For example, one embodiment of the invention includes a processor comprising a store buffer for buffering store operations prior to completion, the store operations to store data to a memory hierarchy; and a store dependence predictor to predict whether load operations should be permitted to speculatively skip over each store operation and responsively setting an indication within an entry associated with each store operation in the store buffer; wherein a load operation checks the indication in the store buffer to determine whether to speculatively execute ahead of each store operation.
    Type: Application
    Filed: June 29, 2013
    Publication date: January 1, 2015
    Inventors: Ho-Seop KIM, Robert S. CHAPPELL, Choon Yip SOO
  • Publication number: 20140379996
    Abstract: An apparatus and method is described herein for providing speculative escape instructions. Specifically, an explicit non-transactional load operation is described herein. During execution of a speculative code region (e.g. a transaction or critical section) loads are normally tracked in a read set. However, a programmer or compiler may utilize the explicit non-transactional read to load from a memory address into a destination register, while not adding the read/load to the transactional read set. Similarly, a non-transactional store is also provided. Here, a transactional store is performed and not added to a write set during speculative code execution. And the store may be immediately globally visible and/or persistent (even after an abort of the speculative code region). In other words, speculative escape operations are provided to ‘escape’ a speculative code region to perform non-transactional memory accesses without causing the speculative code region to abort or fail.
    Type: Application
    Filed: February 2, 2012
    Publication date: December 25, 2014
    Inventors: Ravi Rajwar, Martin G. Dixon, Konrad K. Lai, Robert S. Chappell, Bret L. Toll
  • Patent number: 8838935
    Abstract: In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.
    Type: Grant
    Filed: September 24, 2010
    Date of Patent: September 16, 2014
    Assignee: Intel Corporation
    Inventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell
  • Publication number: 20140189192
    Abstract: An apparatus and method for implementing a multiple page size translation lookaside buffer (TLB). For example, a method according to one embodiment comprises: reading a first group of bits and a second group of bits from a linear address; determining whether the linear address is associated with a large page size or a small page size; identifying a first cache set using the first group of bits if the linear address is associated with a first page size and identifying a second cache set using the second group of bits if the linear address is associated with a second page size; and identifying a first cache way if the linear address is associated with a first page size and identifying a second cache way if the linear address is associated with a second page size.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Inventors: Shlomo Raikin, Oren Hamama, Robert S. Chappell, Camron B. Rust, Han S. Luu, Leslie A. Ong, Gur Hildesheim
  • Publication number: 20140095838
    Abstract: A processor includes a processing unit including a storage module having stored thereon a physical reference list for storing identifications of physical registers that have been referenced by multiple logical registers, and a reclamation module for reclaiming physical registers to a free list based on a count of each of the physical registers on the physical reference list.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: VIJAYKUMAR VIJAY KADGI, JAMES D. HADLEY, AVINASH SODANI, MATTHEW C. MERTEN, MORRIS MARDEN, JOSEPH A. MCMAHON, GRACE C. LEE, LAURA A. KNAUTH, ROBERT S. CHAPPELL, FARIBORZ TABESH
  • Publication number: 20140095814
    Abstract: A processor includes a processing unit including a storage module having stored thereon a table for tracking physical registers in which each store operation stores source data and a memory renaming module for register renaming load operations based on the table.
    Type: Application
    Filed: September 28, 2012
    Publication date: April 3, 2014
    Inventors: MORRIS MARDEN, VIJAYKUMAR VIJAY KADGI, JAMES D. HADLEY, MATTHEW C. MERTEN, GRACE C. LEE, JOSEPH A. MCMAHON, ROBERT S. CHAPPELL, LAURA A. KNAUTH, FARIBORZ TABESH
  • Publication number: 20140075123
    Abstract: In an embodiment, a page miss handler includes paging caches and a first walker to receive a first linear address portion and to obtain a corresponding portion of a physical address from a paging structure, a second walker to operate concurrently with the first walker, and a logic to prevent the first walker from storing the obtained physical address portion in a paging cache responsive to the first linear address portion matching a corresponding linear address portion of a concurrent paging structure access by the second walker. Other embodiments are described and claimed.
    Type: Application
    Filed: September 13, 2012
    Publication date: March 13, 2014
    Inventors: Gur HILDESHEIM, Chang Kian TAN, Robert S. CHAPPELL, Rohit BHATIA
  • Publication number: 20140059333
    Abstract: An apparatus and method is described herein for providing robust speculative code section abort control mechanisms. Hardware is able to track speculative code region abort events, conditions, and/or scenarios, such as an explicit abort instruction, a data conflict, a speculative timer expiration, a disallowed instruction attribute or type, etc. And hardware, firmware, software, or a combination thereof makes an abort determination based on the tracked abort events. As an example, hardware may make an initial abort determination based on one or more predefined events or choose to pass the event information up to a firmware or software handler to make such an abort determination. Upon determining an abort of a speculative code region is to be performed, hardware, firmware, software, or a combination thereof performs the abort, which may include following a fallback path specified by hardware or software.
    Type: Application
    Filed: February 2, 2012
    Publication date: February 27, 2014
    Inventors: Martin G. Dixon, Ravi Rajwar, Konrad K. Lai, Robert S. Chappell, Rajesh S. Parthasarathy, Alexandre J. Farcy, Ilhyun Kim, Prakash Math, Matthew Merten, Vijaykumar Kadgi
  • Patent number: 8631207
    Abstract: Methods and apparatus to provide for power consumption reduction in memories (such as cache memories) are described. In one embodiment, a virtual tag is used to determine whether to access a cache way. The virtual tag access and comparison may be performed earlier in the read pipeline than the actual tag access or comparison. In another embodiment, a speculative way hit may be used based on pre-ECC partial tag match to wake up a subset of data arrays. Other embodiments are also described.
    Type: Grant
    Filed: December 26, 2009
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventors: Zhen Fang, Meenakshisundara R. Chinthamani, Li Zhao, Milind B. Kamble, Ravishankar Iyer, Seung Eun Lee, Robert S. Chappell, Ryan L. Carlson
  • Publication number: 20140006661
    Abstract: A method is described that includes detecting that an instruction of a thread is a locked instruction. The instruction also includes determining that execution of said instruction includes imposing a bus lock. The instruction also include executing a bus lock assistance function in response to said determining, said bus lock assistance function including a function associated with said bus lock other than implementation of a bus lock protocol.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Robert S. Chappell, John W. Faistl, Hermann W. Gartler, Michael D. Tucknott, Rajesh S. Parathasarthy, David W. Burns
  • Publication number: 20140006698
    Abstract: In one embodiment, a cache memory can store a plurality of cache lines, each including a write-set field to store a write-set indicator to indicate whether data has been speculatively written during a transaction of a transactional memory, and a read-set field to store a plurality of read-set indicators each to indicate whether a corresponding thread has read the data before the transaction has committed. A compression filter associated with the cache memory includes a first filter storage to store a representation of a cache line address of a cache line read by a first thread of threads before the transaction has committed. Other embodiments are described and claimed.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Robert S. Chappell, Ravi Rajwar, Zhongying Zhang, Jason A. Bessette
  • Publication number: 20140006739
    Abstract: Embodiments of systems, apparatuses, and methods for temporarily allowing access to a lower privilege level from a higher privilege level.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Inventors: Martin G. Dixon, Gilbert Neiger, Robert S. Chappell, Scott D. Rodgers, Barry E. Huntley
  • Publication number: 20130326201
    Abstract: An apparatus and method are described for processing bit streams using bit-oriented instructions. For example, a method according to one embodiment includes the operations of: executing an instruction to get bits for an operation, the instruction identifying a start bit address and a number of bits to be retrieved; retrieving the bits identified by the start bit address and number of bits from a bit-oriented register or cache; and performing a sequence of specified bit operations on the retrieved bits to generate results.
    Type: Application
    Filed: December 22, 2011
    Publication date: December 5, 2013
    Inventors: Vinodh Gopal, James d. Guilford, Gilbert M. Wolrich, Erdinc Ozturk, Wajdi K. Feghali, Kirk S. Yap, Sean M. Gulley, Martin G. Dixon, Robert S. Chappell
  • Patent number: 8516577
    Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 22, 2010
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Michael S. Bair, David W. Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong, Pankaj Raghuvanshi, Shlomo Raikin, Raanan Sade, Michael D. Tucknott, Igor Yanover
  • Publication number: 20120079232
    Abstract: An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory.
    Type: Application
    Filed: September 24, 2010
    Publication date: March 29, 2012
    Inventors: Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O. Smith, Adrian C. Moga, Scott J. Cape, Wayne A. Downer, Robert S. Chappell
  • Publication number: 20120072984
    Abstract: In one embodiment, the present invention includes a method for identifying a termination sequence for an atomic memory operation executed by a first thread, associating a timer with the first thread, and preventing the first thread from execution of a memory cluster operation after completion of the atomic memory operation until a prevention window has passed. This method may be executed by regulation logic associated with a memory execution unit of a processor, in some embodiments. Other embodiments are described and claimed.
    Type: Application
    Filed: September 22, 2010
    Publication date: March 22, 2012
    Inventors: MICHAEL S. BAIR, David W. Burns, Robert S. Chappell, Prakash Math, Leslie A. Ong, Pankaj Raghuvanshi, Shlomo Raikin, Raanan Sade, Michael D. Tucknott, Igor Yanover