Abstract: A variable length delay line comprises a random-access-memory (RAM) device in which a selected shift between read and write addresses establishes the desired amount of delay.

Abstract: A load is driven by a statically controlled motor drive so as to follow a linear ramp characteristic recurrently, and a jump is caused to occur after each peak of the controlling ramp signal in order to compensate for inertia in the driven load. The inertia compensating jump is adjustable independently from the ramp parameters, and each ramp parameter is adjustable independently from the others as well as from the adjustment of the jump.

Abstract: A symmetrical phase shifter generates two signals shifted symmetrically from an inputted single signal, using digital delay lines.

Abstract: Plug reversal of an induction motor supplied by an N-stage inverter system operating under harmonic neutralization technique is provided by reversing the polarity of the square-shaped voltages combined at .pi./N from each other and by reversing at the same time the sequence of the stages as well as the logic of dissection of the reference time wave. A mirror image of the time scale is effected at the instant of reversal. Digital means are used. Reversible ramp forming generators of the UP-DOWN type are associated in each stage with a phase shifter in order to create the mirror image of the logic controlling the inverter system. A reversible ring counter is used to reverse the sequence of the stages. A reversible pulse generator is used to accommodate an integer number of elementary time intervals in each ramp and between each ramp for the given number of stages.

Abstract: A voltage controlled AC static power supply of the harmonic neutralization type uses symmetrical digital phase shifting in order to reconstruct, with pulses of variable width and predetermined different magnitudes generated by inverters, a sinusoidal wave of fundamental frequency. Phase-shifts are obtained digitally from a single pair of frequency signals. Variable length delay lines are used consisting of random-access-memory (RAM) devices in which a selected shift between read and write addresses establishes the desired amount of delay.

Abstract: In order to maintain a balanced load between power rectifiers operating in parallel within an uninterruptible power system, individual closed loops are established for regulating the direct current voltage at the output of the rectifiers and an open loop generates a reference voltage for each of such regulations. An operational amplifier is used as a current source to develop a current representative of the load in a particular rectifier. Parallel current dissipating resistors between each rectifier line and a floating potential common to all rectifier lines generates a reference voltage which is proportional to the average of such current dissipations and represents the average rectifier load.