Abstract: The present disclosure generally relates to displaying information related to a physical activity. In some embodiments, methods and user interfaces for managing the display of information related to a physical activity are described.

Abstract: An integrated circuit digital device, acting as a master, communicates with at least one peripheral device, acting as a slave, using an enhanced single-node protocol for data, address and control operation. The peripheral device may be selected from any number of different functions. The peripheral device may be packaged in a low pin count integrated circuit package. At a minimum, the peripheral device integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial clock, and data and control input-output (SCIO) terminal. Acknowledgment sequences from both the master and slave devices ensure robust communications therebetween.

Abstract: An integrated circuit digital device, acting as a master, communicates with at least one peripheral device, acting as a slave, using an enhanced single-node protocol for data, address and control operation. The peripheral device may be selected from any number of different functions. The peripheral device may be packaged in a low pin count integrated circuit package. At a minimum, the peripheral device integrated circuit package may have a ground terminal, VSS; a power terminal, VDD or VCC; and a bidirectional serial clock, and data and control input-output (SCIO) terminal. Acknowledgment sequences from both the master and slave devices ensure robust communications therebetween.

Abstract: A dietary supplement product comprises an endocarp of the genera Prunus in ingestible form The endocarp has been lyophilized to remove hydrocyanic acid to a safely ingestible level.

Abstract: A regulated voltage down pump circuit comprises a reference generator circuit receiving a voltage. P channel and N channel device voltage thresholds are measured and compared. A first reference voltage is generated using the largest voltage threshold. A second reference voltage is generated an amount (which may be programmable) above the first reference voltage. The second reference voltage is compared with an output voltage of a pump circuit. When the output voltage is less than the second reference voltage, a clock signal is sent to the pump circuit that generates and pumps up the output voltage to the reference voltage. The pumped voltage at the second reference is then used for logic circuits at reduced power and nearly constant gate delay over voltage, temperature and process variations.

Abstract: A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

Abstract: Disclosed herein is a product comprising a dietary supplement made from the endocarp, exocarp or mesocarp of the genera Prunus, a method of producing the product, one use for the product, and a method of use for the product.

Abstract: Disclosed herein is a product comprising a dietary supplement made from the endocarp, exocarp or mesocarp of the genera Prunus, a method of producing the product, one use for the product, and a method of use for the product.

Abstract: A simplified algorithm for digital signal interpolation and a novel architecture to implement the algorithm in an integrated circuit (“IC”) with significant space constraints are presented. According to embodiments of the present invention, the interpolator is divided into two parts. The first part of the interpolator increases the sample rate by a factor of two and smoothes the signal using a half-band Infinite Impulse Response (“IIR”) filter. The second part of the interpolator increases the sample rate of the signal by a factor of thirty-two using a zero-order-hold (“ZOH”) circuit. In one embodiment, the half-band IIR filter is implemented using an all-pass lattice structure to minimize quantization effects. The lattice coefficients are chosen such that the structure can achieve all filter design requirements, yet is capable of being implemented with a small number of shifters and adders, and no multipliers.

Abstract: An analog-to-digital converter according to the present invention comprising a comparator having first and second inputs, and an output, the comparator comparing an analog input voltage at the first input to a tracking voltage at the second input to place a digital output on the comparator output in response thereto, a voltage switching matrix having an input connected to the output of the comparator and an output, an integrator having an input connected to the output of the voltage switching matrix and an output connected to the second input of the comparator to complete a feedback loop and to provide the tracking signal to the second input of the comparator, and a digital filter coupled to the output of the comparator, the digital filter to form a digital output corresponding to the analog input signal at the first input of the comparator.

Abstract: Integrated circuit devices on a wafer are tested by the use of test circuit on the integrated circuit devices which is connected by means of a grid. The grid is used to enable the test circuitry, and provides an ability to test the devices while still on the wafer. This facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment, an oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the integrated circuits at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.

Abstract: A test circuit is provided for an integrated circuit device, whereby an oscillator is provided on-chip and is activated by a test circuit. The test circuit provides an ability to test the devices while still on the wafer and facilitates burning in the wafer prior to singulating the parts, since it is not necessary to separately establish electrical connections at contact points on the individual integrated circuit devices. The oscillator may be adjusted in speed so that further tests may be effected by changing a test speed through the test circuit. Response of the DUT at different operating speeds is determined by the adjustment of the oscillator speed so that a timing signal used for the testing may be varied.

Abstract: A semiconductor wafer testing fixture facilitates burn-in testing of multiple wafers, whereby individual wafers have an array of individual die or integrated circuit chips with their own test circuitry. The wafer has Vcc and Vss buses provided thereon which are coupled to the individual integrated circuit chips and test circuitry. The fixture has a housing sized to accommodate multiple semiconductor wafers in a selected orientation. The wafers are supported within the housing on corresponding shelves, which provides a back bias voltage to the wafer. The fixture has first and second conductive arms for supplying selected voltages to the Vcc and Vss buses for imparting test cycling of the integrated circuits. The first arm has multiple hands which engage the Vcc buses on the wafers supported on corresponding shelves. Likewise, the second arm has multiple second hands which engage the Vss buses on the wafers supported on corresponding shelves.

Abstract: A patella exercise device for continuously exercising the patella during continuous passive movement of the knee includes a patella contact pad mounted to a (CPM) device for contacting the patella while the knee is moved in flexion and extension by the (CPM) device. The patella contact pad is adapted to contact and push the patella from a neutral anatomical position during operation of the (CPM) device. Depending on the positioning of the patella contact pad with respect to the patella, the patella is either pushed superiorly or inferiorly during flexion and extension of the knee. The patella is then compressed and tightened during the opposite movement. The patella contact pad may be driven by a spring like cam member to exert a predetermined force against the patella. The patella exercise device is useful for therapy of a knee following injury or surgery and helps prevent patella baja.

Abstract: An SRAM having an input address bus, a memory array and coupled sense amplifiers, internal sense amp enable and output data bus enable nodes further includes a circuit for generating an asynchronous address transition signal from a series of address signals received on the input address bus, and a timing and control circuit. The timing and control circuit selects a single address signal and suppresses the other address signals within a predetermined period of time such as the normal cycle time of the SRAM. If the address transition signal includes a pulse train of two or more pulses spaced apart by less than the predetermined time interval, the timing and control circuit generates fixed pulse width sense amp enable and output data bus enable signals corresponding to the last pulse in the pulse train.

Abstract: A continuous passive motion device for achieving full extension of the leg of a patient includes a base and a four-bar articulated limb support member which is mounted for movement on the base. For the articulated limb support member one bar is a femoral support member which is pivotally mounted on the base. Another one of the bars is a tibial support member which is pivotally joined to the femoral support member. Also included in the device is a drive bar which has a first end reciprocally mounted on the base of the device and a second end which is pivotally attached to the femoral support member. A cross bar having a first end pivotally attached to the tibial support member and having a second end pivotally attached to the drive bar interconnects the tibial support member and the drive bar. The device further includes a motor which is connected to the device for reciprocating the first end of the drive bar to alter the configuration of the device for exercising the leg.

Abstract: An integrated circuit sense amplifier includes a pair of complementary inputs for receiving a pair of complementary data signals which are input to a CMOS flip-flop having its output nodes connected to a logic low through a first transistor and its high side connected to a logic high through a second transistor. The first transistor is on when data signals are not being sensed, holding the nodes in a no-current, logic low state. The first transistor turns off and the second transistor turns on just prior to the arrival of a signal, precharging the nodes to an intermediate voltage, permitting the flip-flop to latch more quickly to a full-logic output when the signal arrives. A preamp may be interposed between the complementary inputs and the latch. The preamp inputs and outputs are precharged to voltage levels near or between their anticipated final levels, so that they reach their final levels quickly when the data signal arrives.

Abstract: Integrated circuit devices are fabricated with an additional conductive layer deposited on a semiconductor wafer onto which the semiconductor devices have been formed. The additional layer provides a conductive path to power the test circuits and allows the use of very few electrical connections in order to permit testing of the devices while still on the wafer. The ability to test the devices while still on the wafer facilitates burning in the wafer prior to singulating the parts, since it is not necessary to establish electrical connections at contact points on the individual integrated circuit devices. In one embodiment of the invention, the additional conductive layer is a metal mask and in a further aspect of that embodiment permits external connections to be accomplished at locations outside the die areas, thereby avoiding damage to the integrated circuit devices. Subsequent to testing of the die in wafer form, the metal mask is stripped and the die may be singulated.

Abstract: An apparatus for in-process removal of built-up paraffin and the like from the inner surface of oil pipelines and the like has a combustion section and a heat transfer section. The combustion section includes an air heater, a blower for causing air to flow through the heater and through a heat transfer section, and a conduit for recirculating air from the heat transfer section to the combustion section. The heat transfer section includes a heater shell, and, disposed therewithin, a heat transfer tubing coil connected in an oil pipeline, upstream of built-up material to be removed, oil in the pipeline, being caused to flow through the coil. Heated air from the combustion section flows across the coil in the heater shell in a manner for transfer of heat from the air to the coil and to the oil flowing therewithin, whereby the temperature of the oil in the coil is raised to a predetermined temperature to liquify material built-up on the inner surface of the pipeline and the like to flow with the oil.

Abstract: An integrated circuit using MOSFETs having varying threshold voltages permitting improved performance and reduced area utilization on a monolithic semiconductor chip is produced by selectively varying ion implantation doses in the channels of the MOSFETs. By repeated masking and implanting steps, selected MOSFETs are implanted with differing doses of ions and combinations of doses, thereby forming circuit portions with MOSFETs having threshold voltages tailored to optimize different characteristics associated with different circuit portions.