Patents by Inventor Robert S. Horton
Robert S. Horton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240056693Abstract: Image acquisition and analysis systems for efficiently generating high resolution geo-referenced spectral imagery of a region of interest. In some examples, aerial spectral imaging systems for remote sensing of a geographic region, such as a vegetative landscape are disclosed for monitoring the development and health of the vegetative landscape. In some examples photogrammetry processes are applied to a first set of image frames captured with a first image sensor having a first field of view to generate external orientation data and surface elevation data and the generated external orientation data is translated into external orientation data for other image sensors co-located on the same apparatus for generating geo-referenced images of images captured by the one or more other image sensors.Type: ApplicationFiled: October 23, 2023Publication date: February 15, 2024Inventors: Jack F. Paris, Michael J. Unverferth, Mark Hull, Robert S. Horton, Stephen P. Farrington, Daniel James Rooney
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Patent number: 11800246Abstract: Image acquisition and analysis systems for efficiently generating high resolution geo-referenced spectral imagery of a region of interest. In some examples, aerial spectral imaging systems for remote sensing of a geographic region, such as a vegetative landscape are disclosed for monitoring the development and health of the vegetative landscape. In some examples photogrammetry processes are applied to a first set of image frames captured with a first image sensor having a first field of view to generate external orientation data and surface elevation data and the generated external orientation data is translated into external orientation data for other image sensors co-located on the same apparatus for generating geo-referenced images of images captured by the one or more other image sensors.Type: GrantFiled: June 6, 2022Date of Patent: October 24, 2023Assignee: LandScan LLCInventors: Jack F. Paris, Michael J. Unverferth, Mark Hull, Robert S. Horton, Stephen P. Farrington, Daniel James Rooney
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Publication number: 20230247313Abstract: Image acquisition and analysis systems for efficiently generating high resolution geo-referenced spectral imagery of a region of interest. In some examples, aerial spectral imaging systems for remote sensing of a geographic region, such as a vegetative landscape are disclosed for monitoring the development and health of the vegetative landscape. In some examples photogrammetry processes are applied to a first set of image frames captured with a first image sensor having a first field of view to generate external orientation data and surface elevation data and the generated external orientation data is translated into external orientation data for other image sensors co-located on the same apparatus for generating geo-referenced images of images captured by the one or more other image sensors.Type: ApplicationFiled: June 6, 2022Publication date: August 3, 2023Inventors: Jack F. Paris, Michael J. Unverferth, Mark Hull, Robert S. Horton, Stephen P. Farrington, Daniel James Rooney
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Managing out-of-order memory command execution from multiple queues while maintaining data coherency
Patent number: 9317434Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: GrantFiled: August 3, 2015Date of Patent: April 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
Patent number: 9319040Abstract: A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.Type: GrantFiled: December 23, 2014Date of Patent: April 19, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Huu N. Dinh, Robert S. Horton, Bill N. On
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MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY
Publication number: 20150339230Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: ApplicationFiled: August 3, 2015Publication date: November 26, 2015Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
Managing out-of-order memory command execution from multiple queues while maintaining data coherency
Patent number: 9164908Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: GrantFiled: April 7, 2015Date of Patent: October 20, 2015Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY
Publication number: 20150212941Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: ApplicationFiled: April 7, 2015Publication date: July 30, 2015Inventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
Managing out-of-order memory command execution from multiple queues while maintaining data coherency
Patent number: 9026763Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: GrantFiled: September 27, 2013Date of Patent: May 5, 2015Assignee: International Business Machines CorporationInventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
Managing out-of-order memory command execution from multiple queues while maintaining data coherency
Patent number: 9021228Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: GrantFiled: February 1, 2013Date of Patent: April 28, 2015Assignee: International Business Machines CorporationInventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
Publication number: 20150102846Abstract: A controller sets a selector register of programmable delay signal logic is to a value equal to a required number of clock cycles of delay for signals output from an integrated circuit to an external memory. The controller controls a selection of additional logic along the output path to perform on the delayed signal within a clock cycle without any latency added to the output path by delay signal logic outputting the delayed signal. The controller waits required number of clock cycles after setting the selector register before using the delayed signal output by the delay signal logic onto an output path.Type: ApplicationFiled: December 23, 2014Publication date: April 16, 2015Inventors: HUU N. DINH, ROBERT S. HORTON, BILL N. ON
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Patent number: 8994424Abstract: A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.Type: GrantFiled: March 12, 2013Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Huu N. Dinh, Robert S. Horton, Bill N. On
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Publication number: 20140266356Abstract: A logic unit is configured with least one multiplexor distributed along a delay path of a logic unit, wherein each at least one multiplexor is configured to receive two inputs and output one of the two inputs, wherein each at least one multiplexor is configured to select one of the two inputs to control a particular programmable number of clock cycles of delay added to a signal from 1 to N clock cycles. The logic unit is configured with at least two latches distributed along the delay path of the logic unit, wherein each at least one latch is configured to add a clock cycle of delay, wherein a terminating latch from among the at least two latches is configured to output the signal delayed by the particular programmable number of clock cycles.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: HUU N. DINH, ROBERT S. HORTON, BILL N. ON
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MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY
Publication number: 20140223111Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: ApplicationFiled: February 1, 2013Publication date: August 7, 2014Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
MANAGING OUT-OF-ORDER MEMORY COMMAND EXECUTION FROM MULTIPLE QUEUES WHILE MAINTAINING DATA COHERENCY
Publication number: 20140223115Abstract: Responsive to selecting a particular queue from among at least two queues to place an incoming event into within a particular entry from among multiple entries ordered upon arrival of the particular queue each comprising a separate collision vector, a memory address for the incoming event is compared with each queued memory address for each queued event in the other entries in the at least one other queue. Responsive to the memory address for the incoming event matching at least one particular queued memory address for at least one particular queued event in the at least one other queue, at least one particular bit is set in a particular collision vector for the particular entry in at least one bit position from among the bits corresponding with at least one row entry position of the at least one particular queued memory address within the other entries.Type: ApplicationFiled: September 27, 2013Publication date: August 7, 2014Applicant: International Business Machines CorporationInventors: Robert M. Dinkjian, Robert S. Horton, Michael Y. Lee, Bill N. On -
Patent number: 8341588Abstract: A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures.Type: GrantFiled: October 4, 2010Date of Patent: December 25, 2012Assignee: International Business Machines CorporationInventors: Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Nitin Sharma, Tad J. Wilder, Charles B. Winn
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Publication number: 20120167022Abstract: A chip design methodology and an integrated circuit chip. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).Type: ApplicationFiled: March 2, 2012Publication date: June 28, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. HERZL, Robert S. HORTON, Kenneth A. LAURICELLA, David W. MILTON, Clarence R. OGILVIE, Paul M. SCHANELY, Nitin SHARMA, Tad J. WILDER, Charles B. WINN
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Patent number: 8181148Abstract: A chip design methodology. The methodology includes identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB).Type: GrantFiled: January 15, 2008Date of Patent: May 15, 2012Assignee: International Business Machines CorporationInventors: Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Nitin Sharma, Tad J. Wilder, Charles B. Winn
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Publication number: 20120083913Abstract: A method of forming and electrical structure. The method includes determining that a first semiconductor device requires an engineering change order (ECO). An additional structure layer required to implement the ECO is determined. A first insertion point location for inserting the additional structure layer within the first semiconductor device is selected. The first insertion point location is associated with a second insertion point location within a design for a second semiconductor device. The second semiconductor device is generated in accordance with the first ECO. The second semiconductor device comprises second structures. The second structures comprise same structures as first structures in the first semiconductor device. The second structures are formed in locations within the second semiconductor device that are associated with locations in the first semiconductor device comprising the first structures.Type: ApplicationFiled: October 4, 2010Publication date: April 5, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, David W. Milton, Clarence R. Ogilvie, Nitin Sharma, Tad J. Wilder, Charles B. Winn
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Patent number: 8141028Abstract: A design structure for identifying engineering changeable logic, and replacing the identified engineering changeable logic with flexible logic blocks (FLB). The design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit.Type: GrantFiled: March 25, 2008Date of Patent: March 20, 2012Assignee: International Business Machines CorporationInventors: Robert D. Herzl, Robert S. Horton, Kenneth A. Lauricella, David W. Milton, Clarence R. Ogilvie, Paul M. Schanely, Nitin Sharma, Tad J. Wilder, Charles B. Winn