Abstract: A method and apparatus for controlling data flow between a computer (10) producing a high speed data stream coupled to a buffered storage device including a disc array (43) and to a group of slower speed storage devices including tape drives arranged in a predetermined logical configuration including arrays (42). The system includes controllers (41) that work together such that if one of the controllers fails, the routing between the controllers and the tape drives is switched to the properly functioning controller without the need to involve the computer or operator in the rerouting process thus providing a redundancy of access control and sequencing. The apparatus also includes components which permit a functioning controller to assume control of tape arrays formerly primarily controlled by the failed controller. In addition, the apparatus provides error check and correction generation devices (45, 58) as well as tape storage device configuration circuitry.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remains constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily controlled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.

Abstract: A method and apparatus for controlling data flow between a computer and a group of memory devices arranged in a particular logical configuration. The system includes a group of first level controllers and a group of second level controllers. The first level controllers and the second level controllers work together such that if one of the second level controllers fails, the routing between the first level controllers and the memory devices is switched to a properly functioning second level controller without the need to involve the computer in the rerouting process. The logical configuration of the memory devices remain constant. The invention also includes switching circuitry which permits a functioning second level controller to assume control of a group of memory devices formerly primarily contolled by the failed second level controller. In addition, the invention provides error check and correction as well as mass storage device configuration circuitry.