Abstract: A circuit for comparing two registers has a pair of circuit elements for each bit position and one or the other of these elements conducts if a mismatch occurs between the corresponding register positions. These circuit elements are connected between a first node and a second node. A first circuit pulls up the first node and a second circuit pulls down the second node, and when none of the circuit elements conduct, the first and second nodes have approximately the voltage of the power supply and ground voltage respectively. When any element conducts, the node voltages are approximately equal, at a value established by the voltage dividing effect of the two circuits. An output circuit responds to the voltage between the two nodes to produce a binary voltage signifying a match or mismatch. The first and second circuits are formed by latches that improve the speed of charging and discharging the capacitance of the two nodes when a match or mismatch condition occurs.

Abstract: A circuit for producing a reference voltage, particularly for a voltage regulator, has a current source that produces the desired reference voltage across a string of components. The current source is controlled by a differential amplifier that receives inputs that vary with chip temperature. The differential amplifier increases the reference voltage when the chip temperature increases. When the voltage regulator is used with an FET memory, the increase in the regulator voltage with temperature helps to compensate for an increase in the rate that FET storage cells lose the charge that represents data.

Abstract: A circuit forms a narrow output pulse by charging a first and a second node during the relatively long interval between output pulses. When an initiating pulse is received, both nodes are discharged rapidly. An inverting amplifier which forms the circuit output has its input connected to the second node, and it produces the output pulse as the complement of the voltage level at this node. Time delay elements establish the width of the output pulse. Just before the time for the fall of the output pulse, the first and second nodes are isolated and the second node is then charged to a voltage to turn off the inverting amplifier and drop the output pulse. The initiating pulse is applied to the discharging circuit through a selected one of two paths that have different delays.

Abstract: In a driver circuit for word lines of a semiconductor memory, a CMOS inverter stage and a first FET are connected to opposite terminals of a capacitor to alternately connect the capacitor across the terminals of the power supply for charging the capacitor and between the power supply and the load to add the voltages of the power supply and the capacitor. Second and third FETs form a latch that has one output connected to control the inverter stage and the other output connected to control the first FET. Fourth and fifth FETs are connected to receive a timing signal and to produce true and complement phases for controlling the latch.

Abstract: A multiple input CMOS logic circuit includes a bistable input section with two nodes. In an inactive state, the input section maintains the nodes at opposite CMOS logic levels. In an active state, the nodes are maintained at substantially equal levels positioned between the two CMOS logic levels. The input circuit includes a set of parallel CMOS transistor pairs, cross connected at the nodes. The CMOS pairs are unbalanced by inequality of transistor gate widths. The imbalance causes the input circuit to assume the inactive state. A plurality of input CMOS transistors are connected in parallel between the nodes and receive input signals at their gates. When any of the input transistors is turned on by a change of input signal state, it conducts between the nodes, causing the input circuit to transition to the active state. An output buffer connected to the nodes translates the node levels to CMOS signal levels.

Abstract: An integrated circuit electronic memory array having a plurality of FET memory cells arranged in rows and columns and formed on the same integrated circuit chip with associated support circuits. Each memory cell of the array has a capacitive storage region, an adjacent channel region, and a gate region for controlling the transfer of binary information through the channel region into and out of the capacitive storage region. Each memory cell also includes an offset contact region which contacts an adjacent bit line. The word lines are arranged in rows and the bit lines are arranged in columns, complementary pairs of bit lines being electrically connected to alternate ones of memory cells along each column. A bit line to diffusion capacitance couples each memory cell to the one of the pair of bit lines to which it is electrically not connected. This capacitance boosts the electrical signal written into and read out from the storage capacitor.