Abstract: A delay stage (30,50) receives input signals at input terminal (16) and power from power terminals (12, 14). A detector circuit (30) is connected between power terminals (12, 14) and to the input terminal (16) for receiving the input signal and for generating a detection signal upon detecting a predetermined level of the input signal. A buffer circuit (50) is connected between the power terminals (12, 14) and to the detector circuit (30) for receiving the detection signal while not capacitively loading the detector circuit (30).

Abstract: A clocking system for a self-refreshed dynamic memory (10) for reading data stored in a memory cell (30) and including clocking circuitry (68) includes detecting changes in an address signal (60). The method further includes generating a memory refresh signal (64, 66) in response to detecting changes in the address signal (60). The memory refresh signal (66) is applied to the semiconductor memory circuit (30) for refreshing data stored in the memory cells of the semiconductor memory circuit (30). After the application of the memory refresh signal (66) to the semiconductor memory circuit (30) the address signal (16) is applied to the semiconductor memory circuit (30) for accessing the addressed memory cell to thereby read the data stored therein. The clocking circuitry (68) is reset and precharged during the application of the refresh signal (66) to the semiconductor memory circuit (30).

Abstract: A buffer circuit (10) receives an enable signal to drive power transfer transistors (12,14) which supply power to circuit elements in a semiconductor memory. When an enable signal is driven to a high state the gate terminals of the power transfer transistors (12,14) will be driven positive thereby rendering the transistors conductive. When the enable signal transitions to a low voltage state first and second clock signals (.phi.C1 and .phi.C2) are generated. The action of the clock signals serves to pull a node (20) to one voltage threshold below the reference V.sub.ss. A second node (64) is driven to two thresholds below the reference of V.sub.ss.