Abstract: Disclosed is a system and method for controlling a clutch associated with a solenoid using a pulse width modulated (PWM) signal, which keeps the current through the coil constant over a wide temperature range and fluctuations in line voltage. The system may include a voltage source, a switch (such as a FET), a current sensor, and a processor. The system controls the clutch by sampling the voltage source, sampling the current measured by the current sensor, and computing a duty cycle, which is then used to generate a PWM control signal.

Abstract: A system and method of controlling motor temperature is based on computed motor power dissipation and a thermal model of the motor, rather than a measured motor temperature, in a control loop that limits the motor drive to prevent overheating. An ambient temperature sensor senses the ambient temperature near the motor, and a determination is made of the motor power dissipation. The motor winding temperature is estimated based on the sensed ambient temperature and the determined motor power dissipation. A maximum motor power dissipation that would raise the motor temperature to a predetermined maximum temperature value is determined based on the estimated temperature. The motor power dissipation is limited to a value that is below the determined maximum power dissipation.

Abstract: A delta-sigma modulator for an analog-to-digital converter device and method for reducing a quantization error resulting from differences between the periods of the delta-sigma quantizer clock and the counter clock by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the device and method are particularly effective for measuring the duty cycle of a pulse train from a delta-sigma analog-to-digital converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the delta-sigma modulator and the counter.

Abstract: A delta-sigma modulator for an analog-to-digital converter device and method for reducing a quantization error resulting from differences between the periods of the delta-sigma quantizer clock and the counter clock by using a pulse-width modulator in which the timing of the rising edge of each pulse is controlled by a relatively low-frequency clock signal, and the trailing edge of each pulse is controlled by the input analog signal level. Accordingly, the device and method are particularly effective for measuring the duty cycle of a pulse train from a delta-sigma analog-to-digital converter device when it is undesirable to run the high-frequency clock signal between the pulse-width modulator and the counter, for example when significant physical separation between the delta-sigma modulator and the counter.

Abstract: A Loran-C Receiver Module is provided which utilizes minimum rate sampling means as well as a homodyne receiver at the front end of the Receiver Module to mix down the Loran signal to base band. Once the frequency of the Loran signal is reduced, it is much easier and more economical to perform various functions such as filtering, digitizing, etc. . . . , on the signal.