Abstract: A method and system for dynamic credit sharing in a quick path interconnect link. The method including dividing incoming credit into a first credit pool and a second credit pool; and allocating the first credit pool for a first data traffic queue and allocating the second credit pool for a second data traffic queue in a manner so as to preferentially transmit the first data traffic queue or the second data traffic queue through a link.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: Methods and apparatus to manage communication bus power states are described. In one embodiment, an apparatus comprises a bus including a master node and at least a first slave node, logic to transmit a first power state change request from the master node to the first slave node, logic to receive the first power state change request in the first slave node, and logic to designate the first slave node as the master node when the first slave node denies the first power state change request.

Abstract: A NoDMA cache including a super page field. The super page field indicates when a set of pages contain protected information. The NoDMA cache is used by a computer system to deny I/O device access to protected information in system memory.

Abstract: A system and method for reduced power consumption communications over a physical interconnect is described. In an embodiment, an input/output circuit includes a port to receive a transmission unit via an interconnect, a combining module coupled to the port to append at least one of a first and a second indicator to the transmission unit, a first adder module to generate the first indicator, indicating that the transmission unit is a starting transmission unit of a set of related transmission units, a second adder module to generate the second indicator, indicating that the starting transmission unit of the set of related transmission units has already been received, and logic to determine at least one of the start and end boundaries of the set of related transmission units.

Abstract: A structure referred to as an Active Address Table (AAT) may be used for cache coherence conflict resolution. The AAT may function to detect conflicting coherent requests to the same address and may ensure that each requesting entity receives a copy of the requested cache line in a cache line state-maintaining manner.

Abstract: In one embodiment, the present invention includes a method for performing an operation in a processor of a uniprocessor system, initiating a write transaction to send a result of the operation to a memory of the uniprocessor system, and issuing a global observation point for the write transaction to the processor before the result is written into the memory. In some embodiments, the global observation point may be issued earlier than if the processor were in a multiprocessor system. Other embodiments are described and claimed.