Patents by Inventor Robert Sankman

Robert Sankman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210028087
    Abstract: Embodiments disclosed herein include semiconductor dies and methods of forming such dies. In an embodiment, the semiconductor die comprises a semiconductor substrate, an active device layer in the semiconductor substrate, where the active device layer comprises one or more transistors, an interconnect layer over a first surface of the active device layer, a first bonding layer over a surface of the semiconductor substrate, a second bonding layer secured to the first bonding layer, and a heat spreader attached to the second bonding layer.
    Type: Application
    Filed: July 25, 2019
    Publication date: January 28, 2021
    Inventors: Shrenik KOTHARI, Chandra Mohan JHA, Weihau TANG, Robert SANKMAN, Xavier BRUN, Pooya TADAYON
  • Publication number: 20210013188
    Abstract: Systems and methods for providing a low profile stacked die semiconductor package in which a first semiconductor package is stacked with a second semiconductor package and both semiconductor packages are conductively coupled to an active silicon substrate that communicably couples the first semiconductor package to the second semiconductor package. The first semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a first interconnect pattern having a first interconnect pitch. The second semiconductor package may conductively couple to the active silicon substrate using a plurality of interconnects disposed in a second interconnect pattern having a second pitch that is greater than the first pitch. The second semiconductor package may be stacked on the first semiconductor package and conductively coupled to the active silicon substrate using a plurality of conductive members or a plurality of wirebonds.
    Type: Application
    Filed: September 28, 2017
    Publication date: January 14, 2021
    Applicant: Intel Corporation
    Inventors: Wilfred Gomes, Sanka Ganesan, DOUG INGERLY, ROBERT SANKMAN, MARK BOHR, DEBENDRA MALLIK
  • Publication number: 20210005542
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming electronic packages. In an embodiment, an electronic package comprises an interposer, where the interposer comprises a cavity that passes through the interposer, a through interposer via (TIV), and an interposer pad electrically coupled to the TIV. In an embodiment, the electronic package further comprises a nested component in the cavity, where the nested component comprises a component pad, and a die coupled to the interposer pad by a first interconnect and coupled to the component pad by a second interconnect. In an embodiment, the first interconnect and the second interconnect each comprise an intermediate pad, and a bump over the intermediate pad.
    Type: Application
    Filed: July 3, 2019
    Publication date: January 7, 2021
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Rahul MANEPALLI, Srinivas PIETAMBARAM
  • Publication number: 20200402937
    Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.
    Type: Application
    Filed: June 24, 2019
    Publication date: December 24, 2020
    Applicant: Intel Corporation
    Inventors: Robert Sankman, Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu
  • Publication number: 20200395313
    Abstract: Embodiments disclosed herein include electronic packages and methods of fabricating electronic packages. In an embodiment, an electronic package comprises an interposer, where a cavity passes through the interposer, and a nested component in the cavity. In an embodiment, the electronic package further comprises a die coupled to the interposer by a first interconnect and coupled to the nested component by a second interconnect. In an embodiment, the first and second interconnects comprise a first bump, a bump pad over the first bump, and a second bump over the bump pad.
    Type: Application
    Filed: June 11, 2019
    Publication date: December 17, 2020
    Inventors: Debendra MALLIK, Ravindranath MAHAJAN, Robert SANKMAN, Shawna LIFF, Srinivas PIETAMBARAM, Bharat PENMECHA
  • Publication number: 20200381330
    Abstract: An integrated circuit assembly may be formed comprising at least two integrated circuit packages, wherein the at least two integrated circuit packages share a heat dissipation device. In one embodiment, the at least two integrated circuit packages may be electrically attached to an electronic card to form an intermediate integrated circuit assembly. In a further embodiment, the integrated circuit assembly may comprise at least one intermediate integrated circuit assembly electrically attached to an electronic board.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 3, 2020
    Applicant: Intel Corporation
    Inventors: Chia-Pin Chiu, Robert Sankman
  • Publication number: 20200357744
    Abstract: Embodiments disclose electronic packages with a die assembly and methods of forming such electronic packages. In an embodiment, a die assembly comprises a first die and a second die laterally adjacent to the first die. In an embodiment, the first die and the second die each comprise a first semiconductor layer, an insulator layer over the first semiconductor layer, and a second semiconductor layer over the insulator layer. In an embodiment, a cavity is disposed through the second semiconductor layer. In an embodiment, the die assembly further comprises a bridge substrate that electrically couples the first die to the second die, where the bridge is positioned in the cavity of the first die and the cavity of the second die.
    Type: Application
    Filed: May 7, 2019
    Publication date: November 12, 2020
    Inventors: Khang Choong YONG, Eng Huat GOH, Min Suet LIM, Robert SANKMAN, Telesphor KAMGAING, Wil Choon SONG, Boon Ping KOH
  • Publication number: 20200357721
    Abstract: An integrated circuit structure that includes a first integrated circuit package and a second integrated circuit package is described. The two packages can be stacked above, for example, a printed circuit board. The top package is inverted, such that a first die of that top package is facing a second die of the bottom package. A cooling arrangement is in a gap between the first and second integrated circuit packages, and is thermally coupled to the first and second die. The cooling arrangement is to transfer heat generated by a first die of the first integrated circuit package and a second die of the second integrated circuit package. In some cases, structures comprising electrically conductive material (e.g., metal) are encapsulated by a molding compound or insulator, and extend between a first substrate of the first integrated circuit package and a second substrate of the second integrated circuit package.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Applicant: Intel Corporation
    Inventors: Robert Sankman, MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy
  • Publication number: 20200328139
    Abstract: Embodiments include semiconductor packages and cooling semiconductor packaging systems. A semiconductor package includes a second die on a package substrate, first dies on the second die, conductive bumps between the first dies and the second die, a cold plate and a manifold over the first dies, second die, and package substrate, and first openings in the manifold. The first openings are fluidly coupled through the conductive bumps. The semiconductor package may include a first fluid path through the first openings of the manifold, where a first fluid flows through the first fluid path. The semiconductor package may further include a second fluid path through second openings of the cold plate, where a second fluid flows through the second fluid path, and where the first and second fluids of the first and second fluid paths cool heat providing surfaces of the first dies, the second die, or the package substrate.
    Type: Application
    Filed: April 9, 2019
    Publication date: October 15, 2020
    Inventors: Chia-Pin CHIU, Robert SANKMAN, Pooya TADAYON
  • Publication number: 20200303309
    Abstract: Embodiments disclosed herein include electronic packages for PoINT architectures. Particularly, embodiments include electronic packages that include reinforcement substrates to minimize warpage. In an embodiment, an electronic package comprises, a reinforcement substrate, a plurality of through substrate vias through the reinforcement substrate, a dielectric substrate over the reinforcement substrate, a cavity into the dielectric substrate, and a component in the cavity.
    Type: Application
    Filed: March 18, 2019
    Publication date: September 24, 2020
    Inventors: Robert SANKMAN, Robert MAY
  • Patent number: 10765046
    Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.
    Type: Grant
    Filed: March 1, 2019
    Date of Patent: September 1, 2020
    Assignee: Intel Corporation
    Inventor: Robert Sankman
  • Publication number: 20200211969
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.
    Type: Application
    Filed: December 28, 2018
    Publication date: July 2, 2020
    Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
  • Publication number: 20200186149
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: February 12, 2020
    Publication date: June 11, 2020
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Patent number: 10601426
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Grant
    Filed: September 6, 2018
    Date of Patent: March 24, 2020
    Assignee: Intel Corporation
    Inventors: Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200083890
    Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.
    Type: Application
    Filed: September 6, 2018
    Publication date: March 12, 2020
    Applicant: Intel Corporation
    Inventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
  • Publication number: 20200006305
    Abstract: A semiconductor package includes a first die and a second die. The first die includes a first plurality of compound semiconductor transistors, and where the first die includes a first section of a Power Management Circuitry (PMC). The second die includes a second plurality of transistors that are arranged as a plurality of CMOS (Complementary metal-oxide-semiconductor) circuitries, and where the second die includes a second section of the PMC. The PMC includes a power converter that includes: a plurality of power switches, a plurality of driver circuitries to correspondingly control the plurality of power switches, and a controller to control the driver circuitries. The first section of the PMC in the first die includes the plurality of power switches, and the second section of the PMC in the second die includes at least a part of the controller.
    Type: Application
    Filed: June 28, 2018
    Publication date: January 2, 2020
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Krishna Bharath, Beomseok Choi, Robert Sankman
  • Publication number: 20200006293
    Abstract: Embodiments disclosed herein include an electronics package comprising stacked dies. In an embodiment, the electronics package comprises a first die that includes a plurality of first conductive interconnects extending out from a first surface of the first die. In an embodiment, the first die further comprises a keep out zone. In an embodiment, the electronic package may also comprise a second die. In an embodiment, the second die is positioned entirely within a perimeter of the keep out zone of the first die. In an embodiment, a first surface of the second die faces the first surface of the first die.
    Type: Application
    Filed: June 29, 2018
    Publication date: January 2, 2020
    Inventors: Robert SANKMAN, Sanka GANESAN, Bernd WAIDHAS, Thomas WAGNER, Lizabeth KESER
  • Patent number: 10396046
    Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: Intel Corporation
    Inventors: Yikang Deng, Robert Sankman
  • Publication number: 20190206814
    Abstract: Apparatuses, systems and methods associated with substrate design with a magnetic feature for fully integrated voltage regulator are disclosed herein. In embodiments, a substrate assembly may include a base substrate and one or more interconnect elements located at a first side of the base substrate, the one or more interconnect elements to be coupled to a semiconductor chip having an integrated voltage regulator (IVR). The substrate assembly may further include a magnetic feature located at a second side of the base substrate, the second side being opposite to the first side, wherein the magnetic feature extends along a portion of the second side of the base substrate that is opposite to where the IVR is to be located when the semiconductor chip is coupled to the one or more interconnect elements. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Inventors: Yikang DENG, Robert SANKMAN
  • Publication number: 20190200490
    Abstract: Disclosed are EMI shielded packages, electronic device packages, and related methods. EMI shielded packages are formed by applying an insulating material to a first side of a substrate strip, separating the substrate strip into segments, adhering the insulating material of the segments to a solid conductor, applying a conductive paste around lateral sides of the segments, curing the conductive paste, and cutting through the conductive paste and the solid conductor to form the EMI packages. An electronic device package includes a substrate including electronic circuitry, an EMI shield, and an insulating material insulating the substrate from the EMI shield. The EMI shield includes a solid conductor adhered to the insulating material, and a cured conductive paste at least partially surrounding a lateral edge of the substrate. The cured conductive paste electrically connects the solid conductor to a conductive terminal in a lateral side of the substrate.
    Type: Application
    Filed: March 1, 2019
    Publication date: June 27, 2019
    Applicant: INTEL CORPORATION
    Inventor: Robert Sankman