Abstract: A method and system for in situ cross-linking of polymers, Bitumen, and other materials to produce arbitrary functional or ornamental three-dimensional features using electron beams provided by mobile accelerators comprises defining a desired pattern for imparting on a target area, mapping the target area, defining at least one discrete voxel in the target area according to the desired pattern to be imparted on the target area, assigning an irradiation value to each of the at least one discrete voxels, and delivering a dose of irradiation to each of the at least one discrete voxels according to the assigned irradiation value.

Abstract: A primary device may run a software application requiring a compute task. The primary device may receive statistics from a set of secondary devices over wireless communication links. The primary device may process the statistics to determine whether the compute task will be offloaded to the secondary devices or performed locally. The primary device may generate a distribution scheme for the secondary devices based on the statistics. This may involve modeling first delays associated with transmission of signals from the primary device to the secondary devices, second delays associated with transmission of compute results from the secondary devices to the primary device, and third delays associated with processing resources of the secondary devices. The optimized distribution scheme may minimize overall runtime of the compute task given the modeled delays, scheduling grants for the secondary devices, and a radio resource allocation for the secondary devices.

Abstract: A primary device may run a software application requiring a compute task. The primary device may receive statistics from a set of secondary devices over wireless communication links. The statistics may include parameters associated with the compute and communication capabilities of the secondary devices. The primary device may predict, based on the statistics, an expected performance gain in distributing the compute task to the secondary devices relative to performing the compute task locally. If the expected performance gain is high enough, the primary device may distribute shares of the compute task to the secondary devices over the wireless communication links. If the expected performance gain is low enough, the primary device may perform the compute task locally. If the expected performance gain is moderate, the primary device may update the set of secondary devices and/or may update a coding and distribution scheme for the compute task.

Abstract: A jet valve includes a valve body, a juncture operatively coupled to the valve body. The juncture having a first fluid connection fluidly coupled to a header tank and a second connection fluidly coupled to a storage tank. A spool is movably disposed within the valve body. A jet pump is fluidly coupled to a fuel pump of the header tank via a bleed line. Operation of the fuel pump pressurizes the bleed line and moves the spool to a first position to (i) close a first fluid path between the header tank and the storage tank and (ii) provide a second fluid path between the header tank and the storage tank, the second fluid path through the aperture. Depressurization of the bleed line enables the spring to move the spool to a second position to close the second fluid path and open the first fluid path.

Abstract: A jet valve to control flow of a fluid therethrough is disclosed.

Abstract: A system and method employing at least one semiconductor device, or an arrangement of insulating and metal layers, having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid strand proximate to the detecting region, and a method for manufacturing such a semiconductor device. The system and method can thus be used for sequencing individual nucleotides or bases of ribonucleic acid (RNA) or deoxyribonucleic acid (DNA). The semiconductor device includes at least two doped regions, such as two n-typed regions implanted in a p-typed semiconductor layer or two p-typed regions implanted in an n-typed semiconductor layer. The detecting region permits a current to pass between the two doped regions in response to the presence of the component of the polymer, such as a base of a DNA or RNA strand.

Abstract: A cooked snack food or cooked edible core material, such as roasted nuts, or baked snack chips, while still hot from the cooking step, is tumbled and sprayed with an aqueous solution of a water-soluble, film-forming coating component, such as a maltodextrin. The tumbling and spraying is performed immediately after cooking so that latent heat from the cooked edible core material, reduces the moisture content of the applied aqueous solution to form a dry, thin film coating of the coating component on the edible core material. The need for a separate, subsequent drying step or forced air drying equipment to reduce the moisture content is eliminated by evaporative cooling of the hot cooked snacks and flashing of the applied aqueous coating solution. The dry, coated cooked snack may be cooled to obtain a snack food having a thin, uniform coating which enhances appearance, texture, taste and shelf life.

Abstract: A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local operating systems, each associated with a site controller, enable control of one or more test modules by an associated site controller. Each test module performs testing on a corresponding device-under-test at a test site.

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: There is provided a test emulator for emulating a test apparatus including a plurality of test modules for supplying test signal to devices under test respectively, including: a plurality of test module emulation sections for emulating the plurality of test modules generating the test signal based on different cycles, a control emulation section for emulating a control apparatus for controlling the test of the devices under test, a synchronous emulation section for generating test signal generating timings, at which each of the plurality of test module emulation sections is to generate the test signal in simulation corresponding to cycle time of the test module emulation section, based on instructions from the control emulation section, a timing alignment section for aligning the plurality of test signal generating timings generated by the synchronous emulation section in order of time, and outputting them one by one, and a schedule section for causing the test module emulation section corresponding to one of

Abstract: A distributed operating system for a semiconductor test system, such as automated test equipment (ATE), is described. The operating system includes a host operating system for enabling control of one or more site controllers by a system controller. One or more local operating systems, each associated with a site controller, enable control of one or more test modules by an associated site controller. Each test module performs testing on a corresponding device-under-test at a test site.

Abstract: A semiconductor test system is disclosed which accepts pincards from multiple vendors, each pincard including a local non-volatile memory in which specific calibration data can be stored. Each pincard in the test system may be capable of performing different types of tests on the DUT. Non-volatile memory on the pincard is used to store pincard calibration data, and loadboard and socket related calibration data may also be stored locally in the non-volatile memory of each pincard for use in compensating for signal degradation. Calibration data related to pincard slots (i.e. slot-to-slot skew) may be stored in nonvolatile memory on a test system backplane and used to calibrate slot-to-slot skew of the pincard. Local non-volatile memory may also be used to store commands, data, and error information being generated in or transferred between modules, site controllers and the system controller, so that this information does not need to be regenerated if a system error should occur.

Abstract: An apparatus for supporting and manipulating a testhead for testing semiconductor devices includes a supporting frame, plates adapted to be mounted on opposite sides of the testhead and controllable shafts that connect the supporting frame to the plates. Each plate has an opening in which a flanged bearing is fitted. The testhead is mounted by moving the respective shafts through the flanged bearings within the openings of plates. In this manner, the shafts support the testhead on two fixed pivots. The shafts also provide a fixed axis of rotation about which the testhead can be rotated. The testhead can be locked in a particular position about the fixed rotation axis by a locking pin inserted into one of a plurality of locking holes surrounding the plate opening. A lever arm connected to the locking pin is utilized to change the radial position of the testhead. The testhead is dismounted by unlocking the locking pin and moving the shafts from the flanged bearings.

Abstract: The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved.

Abstract: The present invention is directed to a locking apparatus and loadboard assembly of a semiconductor testing device apparatus. The loadboard assembly includes a printed circuit board containing a device under test and an interface board secured to the bottom of the printed circuit board. The interface board has two members with a space between them. Spacers connect the members to form apertures for contact pins on a test head. The loadboard assembly is placed on top of a locking apparatus which is mounted on the top surface of the test head. The placement of the loadboard on the locking apparatus is done according to two pins of different cross-sections that extend through two holes in the interface board and printed circuit board of the loadboard assembly. When the loadboard assembly is placed on the locking mechanism, rollers mounted on the interface board are received in cam slots of a cam member of the locking apparatus. These rollers follow the cam slots as the cam member is moved.

Abstract: The present invention is directed to a test head Hifix of a semiconductor device testing apparatus that does not require disassembly for maintenance or repair of the semiconductor device testing apparatus. In one embodiment, the test head Hifix of a semiconductor device testing apparatus includes a plate that resides as the top surface of a test head and on which the assembly, loadboard, socket and DUT are mounted. The plate is attached to the test head in an arrangement that allows the plate along with the assembly, loadboard, socket and DUT to be easily moved without completely disassembling the plate, assembly and loadboard from the test head. In one embodiment, the plate is attached or coupled to the test head by hinges.

Abstract: A semiconductor test system is disclosed which accepts pincards from multiple vendors, each pincard including a local non-volatile memory in which specific calibration data can be stored. Each pincard in the test system may be capable of performing different types of tests on the DUT. Non-volatile memory on the pincard is used to store pincard calibration data, and loadboard and socket related calibration data may also be stored locally in the non-volatile memory of each pincard for use in compensating for signal degradation. Calibration data related to pincard slots (i.e. slot-to-slot skew) may be stored in nonvolatile memory on a test system backplane and used to calibrate slot-to-slot skew of the pincard.

Abstract: A system and method employing at least one semiconductor device having at least one detecting region which can include, for example, a recess or opening therein, for detecting a charge representative of a component of a polymer, such as a nucleic acid strand, proximate to the detecting region, and a method for manufacturing such a semiconductor device. The system and method can thus be used for sequencing individual nucleotides or bases of ribonucleic acid (RNA) or deoxyribonucleic acid (DNA). The semiconductor device includes at least two doped regions, such as two n-type regions implanted in a p-type semiconductor layer or two p-type regions implanted in an n-type semiconductor layer. The detecting region permits a current to pass between the two doped regions in response to the presence of the component of the polymer, such as a base of a DNA or RNA strand.