Abstract: A recharging circuit is provided to maintain a high potential for a longer time interval at the output node of a FET driver circuit. The recharging circuit consists of a first FET which is made periodically conductive via a capacitor and periodically recharges a capacitance at the output node. This capacitance is first charged by a strong pulse of the driver circuit. A second FET is provided to prevent a current flow through the first FET and thus the generation of a power dissipating current when the output potential of the driver circuit is low. The gate of the second FET is connected to a supply voltage. Thus, the second FET is conductive when a low potential exists at the output node, transferring that potential to the gate of the first FET which, in turn, does not become conductive since its gate to source voltage is less than its threshold voltage.

Abstract: Utilization of a chip internal clock driver, for capacitive loads such as MOS circuits, which provides in response to an external clock phase adjustable and delayed secondary clock pulses. The delay circuit is an inverter circuit which uses a precharged coupling capacitor whose potential is dynamically increased (boosted) by capacitive coupling the input pulse to approximately twice the supply voltage and which capacitor is subsequently discharged by a constant current thus defining a delay time in a more extended and more precise range.

Abstract: A high performance semiconductor memory read/write data access circuit including a sense amplifier directly coupled to a pair of bit lines is provided with a pair of bit switching devices to enable data communication external to the memory. Control potentials and timing of switching signals are provided in such a manner that only one of the bit switches becomes conductive during reading and writing access to the memory.