Abstract: A charge sensing device with a sense amplifier system implemented in a non-volatile matrix-addressable memory device comprising an electrical polarizable dielectric memory material exhibiting hysteresis, particularly a ferroelectric or electret material. The memory cells of the memory device can be selectively addressed for a write/read operation and the sense amplifier system is used for readout of polarization states of the memory cells.

Abstract: A sense amplifier system for sensing the charge of a charge-storing means (601) comprises first and second charge reference means (600a,600b) connected in parallel and similar to the charge-storing means itself and having respectively opposite polarizations. The charge reference means (600a,600b) and the charge storing means (600) have a common input node (WL), and first and second pseudo-differential reference sense amplifiers (RSA1, RSA2) are connected with output nodes (RBL1, RBL2) of the charge reference means (600a,600b) for generating reference signals to a common reference node (CHREF) connected with a pseudo-differential sense amplifier (SA). The pseudo-differential sense amplifier (SA) has a second input for receiving an output signal from the charge-storing means (601) and generates an output signal indicative of a polarization state of the charge-storing means.

Abstract: A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.

Abstract: A DC offset correction circuit (68) provides DC offset correction within a receiver (50) for receiving and processing a radio frequency signal (28) within a radio communication system (30). The DC offset correction circuit (68) includes a feedback loop (88) for shifting a digital signal (80) by a programmable amount; and a coarse DC offset correction path (104) coupled to the feedback loop (88) for performing coarse DC offset correction.