Patents by Inventor Robert Scott Hartog
Robert Scott Hartog has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130141446Abstract: A method, apparatus and computer readable media for servicing page fault exceptions in a accelerated processing device (APD). A page fault related to a wavefront is detected. A fault handling request to a translation mechanism is sent when the page fault is detected. A fault handling response corresponding to the detected page fault from the translation mechanism is received. Confirmation that the detected page fault has been handled through performing page mapping based on the fault handling response is received.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip J. Rogers, Mark Leather
-
Publication number: 20130141447Abstract: A method of accommodating more than one compute input is provided. The method creates an APD arbitration policy that dynamically assigns compute instructions from a sequence of instructions awaiting processing to the APD compute units for execution of a run list.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Mark Leather, Michael Mantor, Rex McCrary, Sebastien Nussbaum, Philip Rogers, Ralph Clay Taylor, Thomas Woller
-
Publication number: 20130145202Abstract: A method tolerates virtual to physical address translation failures. A translation request is sent from a graphics processing device to a translation mechanism. The translation request is associated with a first wavefront. A fault notification is received within an accelerated processing device (APD) from the translation mechanism that a request cannot be acknowledged. The first wavefront is, stored within a shader core of the APD if the fault notification is received. The first wavefront is replaced with a second wavefront if the fault notification is received, the second wavefront being ready to be executed.Type: ApplicationFiled: December 6, 2011Publication date: June 6, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Sebastien Nussbaum, Rex McCrary, Philip J. Rogers, Mark Leather
-
Publication number: 20130135327Abstract: Provided is a system including a command processor configured for interrupting processing of a first set of instructions executing within a shader core.Type: ApplicationFiled: November 29, 2011Publication date: May 30, 2013Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Nuwan Jayasena, Mark Leather, Michael Mantor, Rex McCrary, Kevin McGrath, Sebastien Nussbaum, Philip Rogers, Ralph Clay Taylor, Thomas Woller
-
Patent number: 8281183Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.Type: GrantFiled: July 27, 2009Date of Patent: October 2, 2012Assignee: ATI Technologies Inc.Inventors: Michael Mantor, Ralph Clayton Taylor, Robert Scott Hartog
-
Publication number: 20120200579Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on an accelerated processing device. A method includes, responsive to an exception upon access to a memory by a process running on a accelerated processing device, whether to preempt the process based on the exception, and preempting, based upon the determining, the process from running on the accelerated processing device.Type: ApplicationFiled: November 4, 2011Publication date: August 9, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Kevin McGRATH, Sebastien Nussbaum, Nuwan Jayasena, Rex McCRARY, Mark Leather, Philip J. Rogers, Thomas R. Woller
-
Publication number: 20120200576Abstract: Methods, systems, and computer readable media for preemptive context-switching of processes on an accelerated processing device are based upon a comparison of the running time of the process and a threshold time quanta. A method includes preempting a process running on an accelerated processing device based upon a running time of the process and a threshold time quanta.Type: ApplicationFiled: November 4, 2011Publication date: August 9, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas Woller
-
Publication number: 20120198458Abstract: Embodiments of the present invention provide a method of synchronous operation of a first processing device and a second processing device. The method includes executing a process on the first processing device, responsive to a determination that execution of the process on the first device has reached a serial-parallel boundary, passing an execution thread of the process from the first processing device to the second processing device, and executing the process on the second processing device.Type: ApplicationFiled: November 30, 2011Publication date: August 2, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Nuwan S. Jayasena, Kevin McGrath, Philip j. Rogers, Thomas Woller
-
Publication number: 20120194528Abstract: Embodiments of the present invention provide a method of preempting a task. The method includes removing the task from the parallel processors via a scheduling mechanism. Responsive to the removing, the method also includes ceasing (i) retrieval of commands from a buffer associated with the task, (ii) dispatch of groups of work-items associated with the task, (iii) dispatch of wavefronts associated with the task, and (iiii) execution of the wavefronts. State information related to the task is saved.Type: ApplicationFiled: November 30, 2011Publication date: August 2, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas R. Woller, Kevin McGrath, Nuwan Jayasena
-
Publication number: 20120194527Abstract: Embodiments described herein provide a method of arbitrating a processing resource. The method includes receiving a command to preempt a task and preventing additional wavefronts associated with the task from being processed.Type: ApplicationFiled: November 30, 2011Publication date: August 2, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Sebastien Nussbaum, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas R. Woller
-
Publication number: 20120194525Abstract: Provided herein is a method including receiving a run list including one or more processes to run on an accelerated processing device, wherein each of the one or more processes is associated with a corresponding independent job command queue. The method also includes scheduling each of the one or more processes to run on the accelerated processing device based on a criteria associated with each process.Type: ApplicationFiled: November 23, 2011Publication date: August 2, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas R. Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip J. Rogers, Mark Leather
-
Publication number: 20120194524Abstract: Methods, systems, and computer readable media embodiments are disclosed for preemptive context-switching of processes running on a accelerated processing device. Embodiments include, detecting by an accelerated processing device a memory exception, and preempting a process from running on the accelerated processing device based upon the detected exception.Type: ApplicationFiled: November 4, 2011Publication date: August 2, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Mark Leather, Philip J. Rogers, Thomas R. Woller
-
Publication number: 20120188259Abstract: Embodiments described herein provide a method including receiving a command to schedule a first process and selecting a command queue associated with the first process. The method also includes scheduling the first process to run on an accelerated processing device and preempting a second process running on the accelerated processing device to allow the first process to run on the accelerated processing device.Type: ApplicationFiled: November 23, 2011Publication date: July 26, 2012Applicant: Advanced Micro Devices, Inc.Inventors: Robert Scott Hartog, Ralph Clay Taylor, Michael Mantor, Thomas Woller, Kevin McGrath, Sebastien Nussbaum, Nuwan Jayasena, Rex McCrary, Philip Rogers, Mark Leather
-
Publication number: 20100017652Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.Type: ApplicationFiled: July 27, 2009Publication date: January 21, 2010Applicant: ATI Technologies ULCInventors: Michael Mantor, Ralph Clayton Taylor, Robert Scott Hartog
-
Patent number: 7577869Abstract: An apparatus with circuit redundancy includes a set of parallel arithmetic logic units (ALUs), a redundant parallel ALU, input data shifting logic that is coupled to the set of parallel ALUs and that is operatively coupled to the redundant parallel ALU. The input data shifting logic shifts input data for a defective ALU, in a first direction, to a neighboring ALU in the set. When the neighboring ALU is the last or end ALU in the set, the shifting logic continues to shift the input data for the end ALU that is not defective, to the redundant parallel ALU. The redundant parallel ALU then operates for the defective ALU. Output data shifting logic is coupled to an output of the parallel redundant ALU and all other ALU outputs to shift the output data in a second and opposite direction than the input shifting logic, to realign output of data for continued processing, including for storage or for further processing by other circuitry.Type: GrantFiled: August 11, 2005Date of Patent: August 18, 2009Assignee: ATI Technologies ULCInventors: Michael Mantor, Ralph Clayton Taylor, Robert Scott Hartog
-
Patent number: 7423644Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.Type: GrantFiled: July 5, 2006Date of Patent: September 9, 2008Assignee: ATI Technologies Inc.Inventors: Vineet Goel, Stephen L. Morein, Robert Scott Hartog
-
Patent number: 7109987Abstract: A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shader processing unit receives primitive indices generated from the primitive information and an auto-index value for each of the plurality of primitive indices. The method and apparatus further includes a plurality of vertex shader input staging registers operably coupled to the shader sequence, wherein the plurality of vertex shader input staging registers are coupled to a plurality of vertex shaders such that in response to a shader sequence output, the vertex shaders generate tessellation factors. The tessellation factors are provided to the vertex grouper tessellator such that the vertex grouper tessellator generates a per-process vector output, a per primitive output and a per packet output during a second pass.Type: GrantFiled: March 2, 2004Date of Patent: September 19, 2006Assignee: ATI Technologies Inc.Inventors: Vineet Goel, Stephen L. Morein, Robert Scott Hartog
-
Patent number: 6728869Abstract: A method and apparatus for avoiding latency in a processing system that includes a memory for storing intermediate results is presented. The processing system stores results produced by an operation unit in memory, where the results may be used by subsequent dependent operations. In order to avoid the latency of the memory, the output for the operation unit may be routed directly back into the operation unit as a subsequent operand. Furthermore, one or more memory bypass registers are included such that the results produced by the operation unit during recent operations that have not yet satisfied the latency requirements of the memory are also available. A first memory bypass register may thus provide the result of an operation that completed one cycle earlier, a second memory bypass register may provide the result of an operation that completed two cycles earlier, etc.Type: GrantFiled: April 21, 2000Date of Patent: April 27, 2004Assignee: ATI International SrlInventors: Michael Andrew Mang, Michael Mantor, Robert Scott Hartog