Abstract: Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Abstract: Briefly stated, the disclosed technology is generally directed to integrated circuit (IC) technology for an IoT processor. In one example, multiple components may be tightly or otherwise integrated onto a single die, e.g., a single monolithic integrated circuit. In one basic example, the components may include a security processing unit and a radio. The components may also include one or more microprocessors (e.g., a processor capable of executing a high-level operating system), microcontrollers, secure memories, encryption components, peripheral interfaces, and/or the like. The security processing unit and/or the configuration of the components may enable, facilitate, or otherwise provide for security features such as tamper resistance, data security, and/or the like.

Abstract: A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

Abstract: Methods, apparatus, and computer-readable storage media are disclosed for applying filtering operations to data transferred as part of a direct memory access (DMA) operation. In one example of the disclosed technology, a system includes a processor, memory, and a direct memory access (DMA) engine coupled to the memory for reading a set of data from a selected range of read memory addresses for the memory without using the processor. A line buffer coupled to the DMA engine is configured to receive DMA read data and temporarily store a portion, but not all of the data set being read by the DMA engine in a line buffer. A digital filter is configured to apply a filtering operation to a windowed subset of the buffered portion of the data set, producing filtered data that is stored to a selected range of write memory addresses for the memory, without using the processor.

Abstract: Apparatus and methods are disclosed for performing mathematical operations that can be applied in a number of processor architectures. In one example of the disclosed technology, a lookup table is configured to return two or more function values based on an input operand of a single processor instruction storing a fixed-point number. A control unit is configured to execute the instruction by addressing the lookup table based on an index portion of the input operand, and an interpolation module is configured to interpolate an output value based on two or more of the returned function values by scaling at least one of the returned function values by a fractional portion of the input operand. In some examples, a second instruction can be used to store the function values in the lookup table.

Abstract: A digital signal processor includes a variable precision hardware pipeline that provides a maximum level of precision using a first plurality of bits for a mathematical representation. The pipeline stages include data registers to store the first plurality of bits. A precision select module selects a level of precision for processing a block of instructions and sets a precision control register. Logic circuitry utilizes the precision control register to gate the clock signal for one or more of the first plurality of bits to reduce the precision of the hardware pipeline. The logic circuitry disables the clock signal for the data latches in the pipeline corresponding to bits to be disabled to reduce the precision. By disabling the clock signal for the data registers, the amount of power consumed by the pipeline can be reduced.

Abstract: Methods and systems for dynamically adjusting credits used to distribute available bus bandwidth among multiple virtual channels, based on the workload of each virtual channel, are provided. Accordingly, for some embodiments, virtual channels with higher workloads relative to other virtual channels may receive a higher allocation of bus bandwidth (more credits).

Abstract: A windshield assembly includes a windshield frame constructed to support a windshield. A plurality of couplers are secured to the windshield frame, and a tower frame for a wakeboard tow rope or cable attachment, radar arch or the like is connected to the windshield frame via the couplers. In one arrangement, the couplers are connected to the wing sections of the windshield frame, and the tower frame extends between the wing sections and above an area defined between the wing sections. The integrated tower frame and windshield simplifies installation for the boat manufacturer while accommodating many varieties of tower and windshield configurations.

Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

Abstract: In a first aspect, a first method is provided. The first method includes the steps of (1) transmitting data on a bus, wherein data is presented on the bus using varying widths; (2) configuring a cyclic redundancy check (CRC) to be performed on the data based on the manner in which the data is presented on the bus; and (3) performing the CRC on the data. Numerous other aspects are provided.

Abstract: An enclosure is removably securable to a support member including a first part of a releasable fastener. The enclosure includes a panel of material sized to enclose the support member. A flexible flap is affixed to the panel, and a second part of the releasable fastener is affixed to the flexible flap. The second part of the releasable fastener is positioned for engagement with the first part when the panel encloses the support member. By affixing the second part of the releasable fastener to the flexible flap, the position of the fastener is adjustable to accommodate panel shrinkage, manufacturing tolerances and the like.

Abstract: A convertible boat top provides a covered area to protect the occupants from environmental concerns such as sun, rain, etc. The convertible top is easily deployed and can be unobtrusively tucked away into a storage area. The top can be provided as original equipment or may be embodied as a kit to adapt an existing boat.

Abstract: A method and apparatus that allow packet based communication transactions between devices over an interconnect bus to be captured to measure performance. Performance metrics may be determined by capturing events at various locations as they pass through the system. Performance may be verified at run time by computing performance metrics for captured events and comparing such metrics to predefined performance ranges and/or self learned performance ranges. Furthermore, embodiments of the present invention provide for dynamic tailoring of bus traffic to generate potential failing conditions. For some embodiments, performance verification as described herein may be performed in a simulation environment.

Abstract: A three-piece hinge supports a two-panel window assembly in a frame. The hinge includes a base member securable to the frame, a first pivot member pivotably coupled with the base member at a first pivot joint, and a second pivot member pivotably coupled with the base member at a second pivot joint spaced from the first pivot joint. The first and second pivot members each have a glass channel for supporting a panel of the two-panel window assembly. In one arrangement, an insert is secured in a pivoting path of the second pivot member to thereby limit a pivot range of the second pivot member. The hinge eliminates the significant machining time required for prior hinge designs, thereby resulting in a simpler less expensive hinge.

Abstract: A processor receives one or more debug commands through a debug port to help debug software being executed by the processor. In response to a first one or more of the debug commands, the processor stops execution of the software, and flushes data from cache memory of the processor to one or more data locations external to the processor. In response to a second one or more of the debug commands, the processor accesses one or more data locations external to the processor, and resumes execution of the software.

Abstract: An apparatus and method to transmit unaligned data over an interface bus while providing the appearance of aligned data transfers to the receiving processor. In a preferred embodiment, an alignment mechanism is provided in the bus interface of the receiving processor to align the data transfers transparent to the receiving processor. The alignment mechanism detects an unaligned transfer in the bus command queue and forms multiple commands of aligned data to send to the processor.

Abstract: In a first aspect, a first method is provided for transferring data using an Infiniband (IB) protocol. The first method includes the steps of (1) receiving a non-IB packet having header data and payload data at a first node of a computer system; and (2) modifying data in the non-IB packet to convert the non-IB packet to an IB packet having header data and payload data. The header data of the non-IB packet is not included in the payload data of the IB packet resulting from the conversion. Numerous other aspects are provided.

Abstract: Methods and apparatuses that may be utilized to dynamically train communications links between two or more devices based on an error detection history are provided. The error detection history may be based on error detection value comparisons (e.g., CRCs) for a sequence of received packets. According to some embodiments, packets may be accepted only if a number (N) of successive packets have been received without errors, while link training may be automatically initiated only if a number (P) of successive packets have been received with errors.

Abstract: Methods and apparatus that allow lost packets on one virtual channel to be retried without requiring all subsequently issued packets, sent over other virtual channels, to be retried. In other words, packet retries may be performed on a “per virtual channel” basis. As a result, other virtual channels, not experiencing lost packets, may not suffer reductions in their bandwidth due to a lost packet occurring on another virtual channel.

Abstract: Methods and apparatus that allow recovery in the event that sequence counts used on receive and transmit sides of a communications link become out of sync are provided. In response to receiving a packet with an expected sequence count from a receiving device, a transmitting device may adjust pointers into a transmit buffer allowing the transmitting device to begin transmitting packets with the sequence count expected by the receiving device.