Abstract: Exemplary techniques for improving the performance of signals transmitted by conductive circuit traces are disclosed. The techniques may be realized as a method comprising the step of reducing a surface roughness of at least one surface of a conductive circuit trace. Alternatively, the techniques may be realized as a circuit board for transmitting at least one signal, the circuit board comprising at least one conductive circuit trace for carrying at least one signal, the at least one conductive circuit trace having at least one polished surface. Further, the technique may be realized as a conductive circuit trace for carrying a signal, the conductive circuit trace comprising conductive material having a plurality of surfaces substantially parallel with a direction of propagation of the signal, wherein the plurality of surfaces includes at least one polished surface having a reduced surface roughness.

Abstract: Exemplary techniques for improving the performance of signals transmitted by conductive circuit traces are disclosed. The techniques may be realized as a method comprising the step of reducing a surface roughness of at least one surface of a conductive circuit trace. Alternatively, the techniques may be realized as a circuit board for transmitting at least one signal, the circuit board comprising at least one conductive circuit trace for carrying at least one signal, the at least one conductive circuit trace having at least one polished surface. Further, the technique may be realized as a conductive circuit trace for carrying a signal, the conductive circuit trace comprising conductive material having a plurality of surfaces substantially parallel with a direction of propagation of the signal, wherein the plurality of surfaces includes at least one polished surface having a reduced surface roughness.

Abstract: An apparatus may include a Serial General Purpose Input Output (SGPIO) initiator device. The SGPIO initiator device may have terminals to receive parallel input signals. The device may also have parallel-to-serial conversion logic to convert the parallel input signals to a serial stream. The device may further have signal ordering logic. The signal ordering logic may be in communication with the terminals and may be in communication with the parallel-to-serial conversion logic. The signal ordering logic may determine an order in which the parallel input signals are provided in the serial stream. Methods of ordering signals within an SGPIO initiator device and systems having SGPIO initiator devices are also disclosed.

Abstract: A method and system for syndrome generation and data recovery is described. The system includes a recovery device coupled to one or more storage devices to recover data in the storage devices. The recovery device includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, and a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product.

Abstract: Provided are a method, system, and article of manufacture for providing data integrity for data streams. Input data streams are received. A parity data stream is generated by computing parity data from the input data streams, wherein the parity data stream comprises data blocks. Data integrity fields are computed for the data blocks, wherein a data integrity field is used to ensure the integrity of a data block for which the data integrity field is computed. The computed data integrity fields are added to the data blocks to generate an output stream.

Abstract: A mixing drum gate for a concrete transport vehicle is described. The gate includes a pivotally mounted plate that abuts the lower portion of the rim of the drum mouth and is biased against it so as to maintain the abutment during rotation, shifting and flexing of the drum. The gate may include a pneumatically controlled opening mechanism that pivots the plate between an open, closed and intermediate positions.

Abstract: A multi-facetted antenna array is disclosed for omnidirectional signalling. The multi-facetted antenna array includes a plurality of abutting facets having a planar region under the patch antenna structures, and curving regions between the planar regions and across the abutting edges of the facets. The planar regions under the patch antenna provide proper RF antenna performance, while the curved regions minimize the size of the assembled array. Further disclosed is a method of mounting the associated RF interface module across an inside corner formed by abutting facets. The disclosed multi-facetted antenna array is particularly useful for overcoming the unsightly size and wind loading problems of multi-facetted antenna arrays known in the art.

Abstract: A method according to one embodiment may include discovering, at least in part, by an integrated circuit of at least one communication protocol via which at least one device external to the integrated circuit is capable of communicating. In this embodiment, the integrated circuit may be capable of communicating in accordance with a plurality of different communication protocols. The method according to this embodiment may also include selecting, at least in part, by the integrated circuit of the at least one communication protocol to use to communicate with the at least one device. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract: A multi-facetted antenna array is disclosed for omnidirectional signalling. The multi-facetted antenna array includes a plurality of abutting facets having a planar region under the patch antenna structures, and curving regions between the planar regions and across the abutting edges of the facets. The planar regions under the patch antenna provide proper RF antenna performance, while the curved regions minimize the size of the assembled array. Further disclosed is a method of mounting the associated RF interface module across an inside corner formed by abutting facets. The disclosed multi-facetted antenna array is particularly useful for overcoming the unsightly size and wind loading problems of multi-facetted antenna arrays known in the art.