Abstract: The present invention discloses an OLED display having a first row of light emitting diodes and a second row of light emitting diodes. A first sensor circuit is coupled to a light emitting diode of the first linear array for detecting an output of the light emitting diode of the first linear array. A second sensor circuit is coupled to a light emitting diode of the second linear array for detecting an output of the light emitting diode of the second linear array. A control circuit simultaneously causes the light emitting diode of the first linear array to emit light and the sensor circuit coupled to the light emitting diode of the second linear array to provide information corresponding to the detected output of the light emitting diode of the second linear array to a sensor reader circuit.

Abstract: A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; one or more clock controllers having clock outputs coupled to the clock inputs of the processing units, the controller operating varying the clock frequency of each processing unit to optimize speed and processing power for a task; and a high-density memory array core coupled to the processing units.

Abstract: In a computer graphics rendering process, a first triangle-shaped primitive and a second triangle-shaped primitive that are connected (that is, they share vertices and a side) are optionally combined to form a quadrangle-shaped primitive. When the first and second triangle-shaped primitives are combined, the resultant quadrangle-shaped primitive is forwarded to a quad-based rasterization process (e.g., a rasterizer or rasterizer subsystem). Otherwise, the first triangle-shaped primitive is forwarded to the rasterization process. The second triangle-shaped primitive may also be forwarded to the rasterization process separate from the first, or it may be used to form a quadrangle in combination with another triangle primitive connected to it. A graphics subsystem could effectively double its throughput of connected triangle primitives by going from three vertices and three edges per primitive to four vertices and four edges per primitive.

Abstract: A low power a reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units, the controller varying the clock frequency of each processing unit to optimize power consumption and processing power for a task.

Abstract: A graphics memory apparatus and methods for the organization, storage and playback of graphics data for display purposes. The image data and overlay data (and/or other graphics data) are organized and stored in the graphics memory in an interleaved fashion so that only one type of graphics data is stored at any one memory address (pixel data or overlay data or other graphics data) and so that preferably full memory capacity is utilized for the area of graphics memory employed. As an example, in a system for displaying eight bits of color image data and two bits of overlay, the overlay data is interleaved with the image data so that four consecutive address locations will contain image data, with preceding or following address location containing the associated overlay data. Therefore, such organization can result in graphics memory efficiency, reduced bandwidth requirements therefor and increased speed with which the contents or portions thereof may be loaded, altered, etc.

Abstract: A graphics memory apparatus and methods for the organization, storage and playback of graphics data for display purposes. The image data and overlay data (and/or other graphics data) are organized and stored in the graphics memory in an interleaved fashion so that only one type of graphics data is stored at any one memory address (pixel data or overlay data or other graphics data) and so that preferably full memory capacity is utilized for the area of graphics memory employed. As an example, in a system for displaying eight bits of color image data and two bits of overlay, the overlay data is interleaved with the image data so that four consecutive address locations will contain image data, with preceding or following address location containing the associated overlay data. Therefore, such organization can result in graphics memory efficiency, reduced bandwidth requirements therefor and increased speed with which the contents or portions thereof may be loaded, altered, etc.