Abstract: A pitch control system for a multibladed variable pitch wind turbine. Each of the turbine blades is pivotally driven about the longitudinal axis thereof independently of the other blades by at least a pair of hydraulic actuators. The actuators are supplied with pressurized hydraulic fluid from a first source thereof under conditions of normal pitch change adjustment. Under conditions wherein feathering of the blades is required, the actuators are supplied with hydraulic fluid from second sources thereof such that one of the actuators associated with each of the blades is supplied with fluid from one second source and a second actuator is provided with fluid from a redundant second source whereby blade feathering may be effected despite a malfunction of one of the redundant sources or one of the actuators.

Abstract: There is disclosed herein a method and apparatus for controlling the power dissipation in a load particularly suitable for use as a dimmer control for lighting circuits. Selected half cycles are applied to a load, such as an incandescent lamp. The number and sequence of the half cycles applied to the load are selected by logic circuitry which, according to the setting of a dimmer control, determines how many complete half cycles out of the total available to apply to the load. Zero crossing switching is used.

Abstract: A large wind turbine rotor blade having a filament wound composite spar securely mounted to a support structure in a manner by which blade loads are transmitted via redundant load paths. Concentric inner and outer metallic adapter sleeves are bonded to the inboard end of the blade spar, and the adapter sleeves and blade spar are joined by a first series of shear bolts and nuts which pass radially through the spar. A second series of radially extending bolts and nuts join the inner and outer sleeves slightly inboard of the end of the spar. The end of the spar is of slightly reduced diameter forming a conical surface which interacts with the inner and outer sleeves to produce a positive lock when the blade is subject to centrifugal loads. The outer sleeve is adapted to be connected to the support structure by conventional techniques such as by a plurality of bolts which extend axially into the butt end of the outer sleeve.

Abstract: In a television signal synchronizer having a coherent memory, it is necessary to modify the writing of data into memory or the reading of data out of memory in order to provide field conversion. In the described apparatus, the reading out of data is always done according to a non-variant sequence determined by the local (studio) reference timing signals. In a first embodiment the read address generator signals are modified so as to read out the stored video signal in accordance with the non-variant write in sequence. In a second embodiment the write address generator signals are modified so as to position the incoming video signal into memory so that it is located in the proper memory position for the non-variant read out sequence.

Abstract: Television synchronizer apparatus includes a coherent memory with preassigned fixed burst phasing of 0.degree. or 180.degree. for each line store of color video image information. The incoming synchronizing components including burst are discarded on the premise that they are well-known repetitive functions. The incoming color video image information is read into the memory coherent with the preassigned burst phasing, thereby significantly reducing the memory storage capacity normally utilized to store sync and burst information.

Abstract: A generally conically shaped cam formed internally of the actuator piston and a follower connected to a rotary shaft serves to provide a position feedback signal within a minimum of space.

Abstract: A MISFET dynamic random access memory chip having 4,096 single transistor, single capacitor storage cells yet packaged in a standard sixteen pin dual inline package is disclosed. Six bit row address and six bit column address data are sequentially multiplexed into row address latches and column address latches through six address pins by sequentially occurring row address and column address strobes. Sixty-four bits of information from an address row are read and transferred to a sixty-four bit column register. One bit of the column register is then selected by the column address decoder so that data is transferred from that bit to a data output latch. Data is transferred into a data input latch and then to the addressed bit of the storage matrix as well as to the addressed column register by a write signal.